xii
I2C Current Address Read ........................................................................ 3-27
I2C Page Write .......................................................................................... 3-29
I2C Sequential Read.................................................................................. 3-31
Refresh/Scrub ................................................................................................... 3-34
CSR Accesses................................................................................................... 3-34
External Register Set ........................................................................................ 3-34
Chip Configuration........................................................................................... 3-35
CSR Architecture ............................................................................................. 3-35
Register Summary ............................................................................................ 3-36
Detailed Register Bit Descriptions ................................................................... 3-38
Vendor/Device Register ............................................................................ 3-39
Revision ID/General Control Register ...................................................... 3-39
SDRAM Enable and Size Register (Blocks A, B, C, D)........................... 3-41
SDRAM Base Address Register (Blocks A/B/C/D) ................................. 3-43
CLK Frequency Register........................................................................... 3-44
ECC Control Register ............................................................................... 3-45
Error Logger Register ............................................................................... 3-49
Error_Address Register ............................................................................. 3-51
Scrub/Refresh Register.............................................................................. 3-51
Scrub Address Register ............................................................................. 3-52
ROM A Base/Size Register....................................................................... 3-53
ROM B Base/Size Register ....................................................................... 3-56
ROM Speed Attributes Registers .............................................................. 3-58
Data Parity Error Log Register ................................................................. 3-60
Data Parity Error Address Register........................................................... 3-61
Data Parity Error Upper Data Register ..................................................... 3-61
Data Parity Error Lower Data Register ..................................................... 3-62
I2C Clock Prescaler Register .................................................................... 3-63
I2C Control Register ................................................................................. 3-63
I2C Status Register.................................................................................... 3-64
I2C Transmitter Data Register .................................................................. 3-65
I2C Receiver Data Register....................................................................... 3-66
SDRAM Enable and Size Register (Blocks E,F,G,H) .............................. 3-66
SDRAM Base Address Register (Blocks E/F/G/H).................................. 3-67
SDRAM Speed Attributes Register .......................................................... 3-68
Address Parity Error Log Register ............................................................ 3-70
Address Parity Error Address Register ..................................................... 3-71
32-Bit Counter........................................................................................... 3-72
External Register Set................................................................................. 3-72
tben Register.............................................................................................. 3-73
Summary of Contents for MVME5100 Series
Page 1: ...MVME5100 Single Board Computer Programmer s Reference Guide V5100A PG2 September 2001 Edition ...
Page 16: ...xvi ...
Page 20: ...xx ...
Page 28: ...xxviii ...
Page 62: ...1 34 Computer Group Literature Center Web Site Product Data and Memory Maps 1 ...
Page 278: ...3 88 Computer Group Literature Center Web Site System Memory Controller SMC 3 ...
Page 288: ...4 10 Computer Group Literature Center Web Site Hawk Programming Details 4 ...
Page 320: ...Index IN 12 Computer Group Literature Center Web Site I N D E X ...