Index
IN-2
Computer Group Literature Center Web Site
I
N
D
E
X
C
cache
coherency restrictions
coherency SMC
support
Cache Control Register
Cache Speed
CHRP memory
CHRP Memory Maps (suggested)
CLK FREQUENCY
CLK Frequency Register
clock frequency
combining, merging, and collapsing
command types
from PCI Master
PPC slave
CONADD and CONDAT Registers
CONFIG_ADDRESS Register
CONFIG_DATA Register
configuration
options on Hawk
registers
requirements on Hawk
type, as used by PHB
configurations
contention
between PCI and PPC
handling explained (PHB)
control bit
descriptions
core frequency
Critical Word First (CWF)
as supported by PCI Master
CSR
accesses to SMC
architecture of SMC
base address
reads and writes
Current Task Priority Register
CWF burst transfers
explained
cycle types
D
data
discarded from prefetched reads
data parity
PPC
Data Parity Error Address Register
Data Parity Error Log Register
Data Parity Error Lower Data Register
Data Parity Error Upper Data Register
data throughput
PPC Slave to PCI Master
data transfer
PPC Master rates
relationship between PCI Slave and
data transfers
decoder
priorities
decoders
address PCI to PPC
for PCI to PPC addressing
PPC to PCI
delayed transactions
PCI Slave
device selection
Disable Error Correction control bit
documentation, related
DRAM
connection diagram
enable bits
size control bits
Summary of Contents for MVME5100 Series
Page 1: ...MVME5100 Single Board Computer Programmer s Reference Guide V5100A PG2 September 2001 Edition ...
Page 16: ...xvi ...
Page 20: ...xx ...
Page 28: ...xxviii ...
Page 62: ...1 34 Computer Group Literature Center Web Site Product Data and Memory Maps 1 ...
Page 278: ...3 88 Computer Group Literature Center Web Site System Memory Controller SMC 3 ...
Page 288: ...4 10 Computer Group Literature Center Web Site Hawk Programming Details 4 ...
Page 320: ...Index IN 12 Computer Group Literature Center Web Site I N D E X ...