4-1
4
4
Hawk Programming Details
Introduction
This chapter contains details of several programming functions associated
with the Hawk ASIC chip.
PCI Arbitration
PCI arbitration must be provided by the host board.
Hawk MPIC External Interrupts
The MVME5100 Hawk MPIC is fully compliant with the industry
standard Multi-Processor Interrupt Controller Specification. Following a
power-up reset, the MPIC is configured to operate in the parallel interrupt
delivery mode on the MVME5100 series:
Table 4-1. MPIC Interrupt Assignments
MPIC
IRQ
Edge/
Level
Polarity
Interrupt Source
Notes
IRQ0
Level
High
PIB (8259) from IPMC761 in PMC Slot 1
3
IRQ1
Level
Low
TL16C550 UART Serial Port 1, 2
1, 4
IRQ2
Level
Low
PCI-Ethernet Device Port 1 (Front panel)
IRQ3
Level
Low
Hawk WDT1O_L / WDT2O_L
5
IRQ4
Level
Low
Thermal Alarm output (TOUT) of Dallas
Semiconductor DS1621
6
IRQ5
Level
Low
PCI-VME INT 0 (Universe LINT0#)
2
IRQ6
Level
Low
PCI-VME INT 1 (Universe LINT1#)
2
IRQ7
Level
Low
PCI-VME INT 2 (Universe LINT2#)
2
IRQ8
Level
Low
PCI-VME INT 3 (Universe LINT3#)
2
Summary of Contents for MVME5100 Series
Page 1: ...MVME5100 Single Board Computer Programmer s Reference Guide V5100A PG2 September 2001 Edition ...
Page 16: ...xvi ...
Page 20: ...xx ...
Page 28: ...xxviii ...
Page 62: ...1 34 Computer Group Literature Center Web Site Product Data and Memory Maps 1 ...
Page 278: ...3 88 Computer Group Literature Center Web Site System Memory Controller SMC 3 ...
Page 288: ...4 10 Computer Group Literature Center Web Site Hawk Programming Details 4 ...
Page 320: ...Index IN 12 Computer Group Literature Center Web Site I N D E X ...