P2 Signal Multiplexing (P2MX)
http://www.mcg.mot.com/literature
3-5
3
MXCLK is the 10MHz bit clock for the time-multiplexed data lines,
MXDO and MXDI.
MXSYNC# is asserted for one bit time at Time Slot 15 by the
MVME260x, MVME270x, MVME360x, or MVME460x. MXSYNC# is
used by the MVME761 transition module to synchronize with the VME
modules.
MXDO is the time-multiplexed output line from the main board and
MXDI is the time-multiplexed line from the MVME761 transition module.
A 16-to-1 multiplexing scheme is used with a 10MHz bit rate.
MXSYNC# is clocked out using the falling edge of MXCLK and MDXO
is clocked out with the rising edge of the MXCLK. MXDI is sampled at
the rising edge of MXCLK (the transition module synchronizes MXDI
with MXCLK’s rising edge).
The timing relationships among MXCLK, MXSYNC#, MXDO, and
MXDI are illustrated in
.
11
Reserved
11
DSR1
12
Reserved
12
DCD1
13
Reserved
13
RI2
14
Reserved
14
DSR2
15
Reserved
15
DCD2
Table 3-1. P2 signal multiplexing sequence
MXDO
(from the
MVME260x/MVME270x/MVME360x/
MVME460x)
MXDI
(from the MVME761)
Time Slot
Signal Name
Time Slot
Signal Name
