Setting Up the System Clock Speed
13
Figure 8. Programming Model of PCTL0
Figure 9. Programming Model of PCTL1
5.1
Setting Up the PLL in Software
The clock frequency of the SC140 can be set up either in software or in hardware. This section describes
how to set the SC140 in the Software Development Platform (SDP) to operate at 300 MHz using these two
alternatives. The C code to set up the PLL to 300 MHz is shown in Code 6.
Code 6. C Code to Set Up the PLL to 300 MHz
#include “EOnCE_registers.h”
void PLL_setup_300MHz()
{
asm("move.l #$80030003,PCTL0");
asm("move.l #$00010000,PCTL1");
}
To set up the SC140 for operation at 300 MHz, the registers PCTL0 and PCTL1 should be set to the values
0x80030003 and 0x00010000, respectively. These settings are explained in Table 3.
Table 3. Settings of PCTL0 and PCTL1
Field
Setting
(binary value)
Description
PCTL0.PEN
1
PLL enabled. The internal clocks are derived from the PLL output
PCTL0.RCP
0
PLL locks with respect to the positive edge of the reference clock
PCTL0.MFN
000000000
MFN = 0
PCTL0.MFI
1100
MFI = 24
PCTL0.MFD
000000000
MDF = 1
PCTL0.PD
0011
PD = 4
PCTL1.COE
1
Clock out pin receives output
PCTL1.PODF
0
PODF = 1
