Motorola PPC/PMC-8260/DS1, Reference Manual

Page 1: ...PPC PMC 8260 DS1 Reference Guide P N 6806800B10A July 2006 ...

Page 2: ...ntent hereof without obligation of Motorola to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to the Motorola Embedded Communications Computing Web site The text itself may not be published commercially in print or electronic form edited translated or otherwise altered with...

Page 3: ...er Sources of Information Safety Notes Sicherheitshinweise 1 Introduction Features 3 Variants 5 PMC 8260 DS1 SC F 5 Variant Features 5 Restrictions 5 PMC 8260 DS1 H110 F 5 Variant Features 6 Restrictions 6 Standard Compliances 7 Ordering Information 8 ...

Page 4: ...C Requirements for PPC PMC 8260 DS1 6 Switch Settings 7 Allowed Product Combinations 8 Installing a PMC Module 10 Installation Procedure 11 Removal Procedure 13 Software Upgrades and Accessories 14 3 Indicators and Connectors Front Panel 3 Connectors 4 Serial Connector 4 Line Interface Connector 5 LEDs 5 On Board Connectors 7 PMC I O 8 JTAG Debug 10 4 Firmware Introduction 3 Features 3 ...

Page 5: ...ontrol Status Register Section 16 Primary Booter Commands 18 Starting the Primary Booter 20 Reading and Writing 22 Programming a Boot Image into Boot Flash 23 Obtaining Results from the Power On Self Test 24 Requirements 24 POST Result Storage Area 24 Global Results 25 Checksum 26 POST Progress Information 26 Device Specific Results 26 Code Examples 30 Data Definitions 30 Resetting the PPC PMC 826...

Page 6: ...iguration 11 PCI Lockout 11 Opening More Windows in the PCI Target Channel 12 Accessible 60x Bus Resources 13 Opening Windows in the 60x Bus Slave Channel 14 SDRAM and its Performance 15 SDRAM Machine Memory Controller 15 SSRAM Information for Support Package Programmers 16 I O Bus 18 Boot Flash PROM 18 Programming the Boot Flash when PowerQUICC II is in Reset 19 Memory Map when PowerQUICC II is i...

Page 7: ...nnel Configuration About this Chapter 3 Synchronizing the Clock 4 Configuring the PPC PMC 8260 DS1 as Clock Master 4 Configuring the PPC PMC 8260 DS1 as Clock Slave 6 Routing Time Division Multiplex Timeslots 7 PowerQUICC II Port Functions on PPC PMC 8260 DS1 11 A Troubleshooting Index ...

Page 8: ...viii PPC PMC 8260 DS1 ...

Page 9: ... Reference Platform 9 Indicators and Connectors Table 8 Availablility of Serial I O Channels 4 Table 9 LED States During Power Up 5 Firmware Table 10 Steps Performed During Power Up 6 Table 11 ROM Image Configuration Section 10 Table 12 PCR Register Settings 13 Table 13 Primary Booter CSR Section 16 Table 14 Primary Booter Commands and Parameters 18 Table 15 POST Result Storage Area 25 Table 16 PO...

Page 10: ...s on 60x Bus PowerPC Bus 15 Table 29 SSRAM Timing Performance at 66 MHz T 15 15 nsec 16 Table 30 SSRAM Address on 60x Bus Local Bus 17 Table 31 Flash PROM Access on 60x Bus 18 Table 32 Memory Map when PowerQUICC II is in Reset 21 Table 33 Flash PROM Access from PCI Bus with PowerQUICC II Held in Reset 21 Table 34 T8105 Access on 60x Bus 22 Table 35 Framer Access on 60x Bus 23 Table 36 LED Control ...

Page 11: ... 7 PMC I O and JTAG Debug Connector 7 Figure 8 PMC I O Connector Pinout for PMC 8260 DS1 SC F 8 Figure 9 PMC I O Connector Pinout for PMC 8260 DS1 H110 F 9 Figure 10 JTAG Debug Connector 10 Figure 11 JTAG Debug Connector Pinout 11 Firmware Figure 12 Flowchart of the PPC PMC 8260 DS1 Firmware Power Up Sequence 5 Figure 13 Memory Layout of the Primary Booter 16 Memory Map and Devices Figure 14 Block...

Page 12: ...S1 Figure 17 Local TDM Clocking Structure 5 Figure 18 Connection of TDM Channels 7 Figure 19 Switching of TDM Channels 8 Figure 20 Connection of Local TDM Streams 9 Figure 21 Connection of Data Lines in Inter TDM Link 10 ...

Page 13: ... through F e g used for addresses and offsets 00002 Same for binary numbers digits are 0 and 1 x Generic use of a letter n Generic use of numbers Bold Character format used to emphasize a word Courier Character format used for on screen output Courier Bold Character format used to characterize user input Italics Character format for references table and figure descriptions text Typical notation us...

Page 14: ...ipheral Component Interconnect CPM Communication Processor Module CPU Central Processing Unit CS Chip Select CSR Control Status Register CSU Channel Service Unit DMA Direct Memory Access DRAM Dynamic Random Access Memory EMC Electromagnetic Compatibility ESD Electrostatic Discharge FAE Field Applications Engineer FCC Federal Communications Commission GND Ground GPCM General Purpose Chip Select Mod...

Page 15: ... Linear Feet per Minute LSB Least Significant Bit MAC Media Access Control MMU Memory Management Unit MPTPR Memory Periodic Timer Prescaler Register MSB Most Significant Bit MSR Machine State register MTP Message Transfer Protocol PB Processor Bus PCA Printed Circuit Assembly PCI Peripheral Component Interconnect PCM Pulse Code Modulation PCR Power Up Control Register PMC PCI Mezzanine Card POST P...

Page 16: ...Interface SMC Serial Management Controller SMD Surface Mounted Device SSRAM Synchronous Static Random Access Memory SYPCR System Protection Control register TA Transfer Acknowledge TDI Test Data In TDM Time Division Multiplex TDO Test Data Out TNV Telecommunication Network Voltage TSA Time Slot Assigner TSR Test Status Register UPM User programmable Machine VME Versa Module Eurocard VPD PCI Vital ...

Page 17: ...ur manuals and how we can make them better Mail comments to Motorola GmbH ECC Embedded Communication Computing Lilienthalstr 15 85579 Neubiberg Munich Germany ECCRC motorola com In all your correspondence please list your name position and company Be sure to include the title part number and revision of the manual and tell how you used it ...

Page 18: ...errupt Structure 214293 AB April 2001 Added note to the Routing Time Division Mul tiplex Timeslots section Editorial changes 215165 AA August 2001 Corrected information in the Front Panel sec tion Changed Table 2 Ordering Information Removed information on PMC 8260 DS1 N variant Added note to the Action Plan section Corrected setting of SW1 4 in Table 5 Default Switch Settings for SW1 Corrected Fi...

Page 19: ...tion removed section Location Overview modified the Installing a PMC Module section removed Figure 11 Inter TDM Link Signals on PMC I O Connec tor and integrated information in Figure 10 PMC I O Connector Pinout for PMC 8260 DS1 H 110 RLH modified Figure 8 PMC I O Connector Pinout for PMC 8260 DS1 SC F and Figure 9 PMC I O Con nector Pinout for PMC 8260 DS1 H110 F renamed figure 10 to PMC I O Conn...

Page 20: ...ssible clock sources in the Configuring the PMC 8260 DS1 as Clock Masterî section editorial changes 222192 AA January 2004 Changed manual type from Installation Guideî to Reference Guide updated Other Sources of Informationî page xxii added PCI interface data to the Features section modified Figure 1 Function Blocks added the Carrier Board Signaling Level Requirements section added PCI bus and sig...

Page 21: ...tion Guide StackWare Rel 4 2 0 Release Notes Distributed MTP 3 Rel 5 x Programmer s Guide Distributed MTP 3 Rel 5 0 1 Release Notes DMTP 3 Rel 5 0 1 for MontaVista Linux Carrier Grade Edition Installation Guide MPC8260 PowerQUICC II User s Manual MPC8260 PowerQUICC II User s Manual MPC8260A HiP4 Supplement MPC826xA HiP4 Family Hardware Specification IEEE ieee org IEEE Standard Physical and Environ...

Page 22: ...xxii PPC PMC 8260 DS1 ...

Page 23: ...to install maintain and operate the PPC PMC 8260 DS1 The information given in this manual is meant to com plete the knowledge of a specialist and must not be taken as replacement for qualified personnel EMC The module has been tested in a standard Motorola system and found to com ply with the limits for a Class A digital device in this system pursuant to part 15 of the FCC Rules respectively EN 55...

Page 24: ...you have to take before turn ing off the power Take those steps Finally turn off the power Before touching modules or electronic components make sure that you are working in an ESD safe environment The 3 3V and 5V power supplies of the PMC module carrier board must ramp up simultaneously in about max 20 msec Otherwise the PMC mod ule may be damaged The power supply circuits on VME bus carrier boar...

Page 25: ... dangerous Do not operate the product outside the specified environmental limits High humidity and condensation may cause short circuits Make sure the product is completely dry and there is no condensation of water on any parts of the board s surface before applying power Do not operate the product below 0 C RJ 45 Connector Connecting a telephone or Ethernet to the RJ 45 connector of the PMC 8260 ...

Page 26: ...xxvi PPC PMC 8260 DS1 ...

Page 27: ...ürfen nur von durch Motorola ausgebildetem oder im Bereich Elektronik oder Elektrotechnik qualifiziertem Personal durchgeführt werden Die in diesem Handbuch enthaltenen Informationen dienen ausschließlich dazu das Wissen von Fachpersonal zu ergänzen können dieses jedoch nicht ersetzen EMV Das PMC Modul wurde in einem Motorola Standardsystem getestet Es erfüllt die für digitale Geräte der Klasse A ...

Page 28: ...Boards vor dem Abschalten des Stroms durchgeführt werden müssen Führen Sie die Schritte aus Schalten Sie den Strom ab Ist mehr als ein PPC PMC 8260 DS1 auf einem VME Board installiert so kann dies zu einer Überlastung des Konverters führen der die 3 3 Volt Spannungsversorgung auf dem VME Board generiert und das Board wird beschädigt Stellen Sie deshalb sicher daß die 3 3 Volt Versorgung des VME Bo...

Page 29: ...ist gefährlich Betreiben Sie das PPC PMC 8260 DS1 nur innerhalb der angegebenen Gren zwerte für die relative Luftfeuchtigkeit und Temperatur da durch hohe Luft feuchtigkeit und Kondensation Kurzschlüsse entstehen können Stellen Sie vor dem Einschalten des Stroms sicher dass sich auf dem PPC PMC 8260 DS1 kein Kondensat befindet und betreiben Sie das PPC PMC 8260 DS1 nicht unter 0 C RJ 45 Stecker We...

Page 30: ...xxx PPC PMC 8260 DS1 ...

Page 31: ...1 Introduction ...

Page 32: ......

Page 33: ...velopment efforts when enabling communication with a telecommunication management network Motorola offers MTP 2 LAPD Frame Relay protocol stacks for the operating systems Solaris VxWorks and Linux Revision 1 3 of the PPC PMC 8260 DS1 provides the following improvements compared to Revision 1 2 New HiP4 derivate of PowerQUICC II is used which provides an increased core frequency of 300 MHz and an i...

Page 34: ...e below Tundra PowerSPAN II PCI Bridge 33 66 MHz SDRAM 64 Bit 64 MByte 66 MHz SSRAM 32 Bit 1 MByte 66 MHz Boot Flash 2 MByte Agere T8105 H 110 or SCbus Inter TDM Link Line 1 Line 2 Motorola MPC8260 300 MHz Framer PM4351 Framer PM4351 PCI Bus 32 64 bit 33 66MHz 60x Bus Local Bus Figure 1 Function Blocks ...

Page 35: ...ant Features The PMC 8260 DS1 SC F has the following features Two line interfaces on the front panel SCbus specification compliant termination and clocking Backwards compatible hardware to Motorola PMC 860 E1 T1 module Restrictions The PMC 8260 DS1 SC F has the following restrictions Can only be used in PMC slot 1 due to SCbus load restrictions No SCbus ID signals available No inter TDM link conne...

Page 36: ...rmination and redundant clocking PMC slot1 TDM streams may be routed to PMC slot 2 via the inter TDM link connection or via the PCI bus CT Management bus CT_MC is availabe via the PowerQUICC II serial inter face SCC3 Restrictions The PMC 8260 DS1 H110 F variants have the following restrictions Front panel line interfaces of PMC 8260 DS1 H110 F variant only support short haul On the carrier boards ...

Page 37: ...BR4 E1 120 Ohm Telecom requirements IEC 68 2 1 2 3 13 14 Climatic environmental requirements The PPC PMC 8260 DS1 can only be used in a restricted temperature range see the Environmental Requirements section on page 2 4 for details IEC 68 2 6 27 32 Mechanical environmental requirements ANSI IPC A 610 Rev C Class 2 ANSI IPC 7711 ANSI IPC 7721 ANSI J 001 003 Manufacturing Requirements Note The produ...

Page 38: ...CC II based PMC module H110 bus 300 MHz 64 MByte SDRAM 1 MByte SSRAM Software Accessories PPC PMC 8260 DS1 107405 Tornado 2 0 BSP PMC 8260 Tornado 2 0 Board Support Package BSP for PPC PMC 8260 DS1 106881 SW STACK MTP2 R4 Motorola MTP 2 protocol software package including control configuration and test func tions Solaris 2 6 2 7 and 8 64 bit mode VxWorks 5 4 Tornado 2 0 and Linux 2 4 x driver RTU ...

Page 39: ...2 Installation ...

Page 40: ......

Page 41: ...on Plan In order to install the PMC module the following steps are necessary and are described in detail in the sections of this chapter Startinstallation Installationfinished Makesurerequirementsaremet Checkifswitchsettingsare correct InstallPMCmodule ...

Page 42: ...which means that in T1 mode the interfaces do not sup port long haul required for public networks To be able to operate the PPC PMC 8260 DS1 in a public network you need a CSU channel service unit Carrier Board Signaling Level Requirements The PPC PMC 8260 DS1 supports signaling levels 3 3V and 5V and therefore is a universal PMC module Make sure that your carrier board has a signaling level of 3 ...

Page 43: ...o 95 at 40 C Altitude 300 m to 3 000 m 300 m to 13 000 m Vibration 10 to 15 Hz 15 to 150 Hz 2 mm amplitude 2 g 5 mm amplitude 5 g Shock 5 g 11 ms halfsine 15 g 11 ms halfsine Free Fall 100 mm 3 axis 1200 mm all edges and corners packed state Power Requirements The power supply must meet the power requirements of the carrier board and the PPC PMC 8260 DS1 module For the power requirements of the ca...

Page 44: ...the FCC registration for this equip ment If requested provide information to your telephone company If your PPC PMC 8260 DS1 causes harm to the telephone network the telephone company may discontinue your service temporarily If possible they will notify you in advance But if advance notice is not practical you will be notified as soon as possible You will be advised of your right to file a complai...

Page 45: ...ate into the flash from PCI bus Otherwise the board does not boot Table 5 Default Switch Settings for SW1 Switch Number Description SW1 1 PowerSpan power up option boot from 60x PCI OFF default Normal operation ON Boot from PCI Lockout bit cleared 2 Flash programming via PCI bus OFF default Normal operation ON Enable boot Flash programming via PCI bus 3 Reserved must be OFF 4 Enable MPC8260 COP in...

Page 46: ...Rev 2 0 and later 1 PowerCoreCPCI 6750 Rev 2 x supports two PMC modules only if it has a certain PCB revision For further information see Table 7 Revisions Supported by Reference Platform on page 2 9 1 H 110 F H 110 F H 110 bus 2 2 4 Slot 1 yes Slot 2 yes Yes MFIO 120 H 110 F H 110 F H 110 bus 2 2 4 Slot 1 yes Slot 2 yes Yes Note As described in the table above the reference platform PowerCoreCP C...

Page 47: ...4 R 2 106476 PPC PowerCoreCPCI 6750 64 233 L512 4 R2 Rev M 106349 PCA PowercoreCPCI 6750 0 400 L1024 8R 2 106477 PPC PowerCoreCPCI 6750 128S 400 L1M 8 R2 106478 PPC PowerCoreCPCI 6750 64S 400 L1M 8 R2 Rev H 107398 PCA PowercoreCPCI 6750 0 500 L1M 8 2 0 107344 PPC PowerCoreCPCI 6750 128S 500 L1M 8R2 Installation Allowed Product Combinations PPC PMC 8260 DS1 2 9 ...

Page 48: ...pped without modules installed the front panel cutouts are covered by blind panels to ensure proper EMC shielding Caution Be sure to mount only allowed combinations of PPC PMC 8260 DS1 vari ants see the Allowed Product Combinations section on page 2 8 Other wise damage to PMC module or carrier board may occur The PPC PMC 8260 DS1 is not certified for the use with TNV 1 circuits Telecommunication N...

Page 49: ...he PMC module check which PMC slot s is are sup ported on the used carrier board see see the Allowed Product Combina tions section on page 2 8 1 Check all boards installed in system for steps to be taken before turning off power 2 Take those steps 3 Turn off power 4 Remove carrier board from system according to carrier board s Installa tion Guide if it is already installed in system 5 Remove blind...

Page 50: ... of carrier board Figure 3 Installation Example with PowerCoreCPCI 6750 Rev 2 x 9 Fasten four screws delivered with PMC module 10 Install carrier board according to carrier board s Installation Guide 11 Attach interface cables 12 If not installing a hot swappable carrier board switch power on ...

Page 51: ...p carrier board start procedure with step 1 1 Check all boards installed in system for steps to be taken before turning off power 2 Take those steps 3 Switch off system 4 Remove carier board from system according to carrier board s Installa tion Guide 5 Remove screws holding respective PMC module 6 Disconnect PMC module carefully from slot 7 Close front panel gap at free slot with blind panel ...

Page 52: ...MTP 2 LAPD and Frame Relay Support is available for the operating systems Solaris 2 6 2 7 and 8 VxWorks 5 4 Tornado 2 0 and Linux Kernel 2 4 x For possible combinations of protocol operating system and carrier board ask your local Motorola sales representative For installation information refer to the respective Installation Guide and for using the protocol functions refer to the respective Progra...

Page 53: ...3 Indicators and Connectors ...

Page 54: ......

Page 55: ...C 8260 DS1 3 3 Front Panel The interface connectors and LEDs available on the different variants can be seen in the following figure LINE 1 LINE 2 L1 L2 S E R Motorola Serial Interface Line Interfaces User Programmable LEDs Figure 4 Front Panels ...

Page 56: ... O Port Connector Pinout The following table shows the availability of serial I O channels Table 8 Availablility of Serial I O Channels I O Channel MicroD Sub on Front Pan el PMC User I O SMD JTAG De bug P4 PowerQUICC II SCC_1 UART RS 232 only on H110 F and SC F variants RS 232 assembly option PowerQUICC II SMC_1 UART RS 232 PowerQUICC II SCC_2 ETH SCC2 Ethernet mode assembly option instead of RS ...

Page 57: ...put Reserved Tx Ring Output Tx Tip Output Reserved Reserved Reserved Figure 6 Front Panel RJ 45 Interface Connector Pinout LEDs The PPC PMC 8260 DS1 offers two user programmable LEDs L1 and L2 for lo cation see Figure 4 Front Panels on page 3 3 which can take the states off red green and yellow At power up they show the state of the power up se quence Furthermore you can control the status of the ...

Page 58: ...r 2 test running Yellow Off Framer 3 test running Off Yellow Framer 4 test running Yellow Off T8105 test running Off Yellow POST complete Yellow Green Executing ROM image end of boot sequence Green Off Primary booter Idle loop Red Green dimmed flashing Flash erase write operation ongoing Red Yellow flashing Before execution of uploaded image Green Off Table 9 LED States During Power Up cont State ...

Page 59: ... On Board Connectors Apart from the three standard PMC connectors the PPC PMC 8260 DS1 offers the PMC I O and the JTAG Debug connector The figure below shows the location of these two connectors JTAG Debug Connector P4 PMC I O Figure 7 PMC I O and JTAG Debug Connector ...

Page 60: ... GND SC_D10 SC_D08 GND SC_D05 SC_D03 SC_D01 SC_D00 SC_FR_COMP SCLK SCLKx2 n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c SC_MC SC_D14 SC_D12 SC_D11 SC_D09 SC_D07 SC_D06 SC_D04 SC_D02 GND SC_CLKFAIL SC_REF8K GND n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c Figure 8 PMC I O Connector Pinout for PMC 8260 DS1 SC F Note Pins 27 29 30 31 and 32...

Page 61: ...K_PMC_OUT BTFP_PMC_OUT T8105_LDO 10 T8105_LDO 11 FET_CTRL_B EARLY_PMC T8105_LDI 10 T8105_LDI 11 n c CT_D15 CT_D13 GND CT_D10 CT_D08 GND CT_D05 CT_D03 CT_D01 CT_D00 FR_COMP SCLK SCLKx2 FET_CTRL_A CT_C8_A CT_NETREF_2 BTCLK_PMC_IN BTFP_PMC_IN PQ2_C2_L1RXD_IN PQ2_D2_L1RXD_IN n c n c PQ2_C2_L1TXD_OUT PQ2_D2_L1TXD_OUT n c n c n c n c n c n c n c n c Indicators and Connectors On Board Connectors PPC PMC ...

Page 62: ...asy connection of a Standard Motorola Third Party COP Interface Emulator Additionally it provides a second RS 232 interface for debugging convenience PowerQUICC II SMC1 interface and the necessary sup ply voltages The COP interface port can be used for Program flow tracking Internal watch point and breakpoint generation Emulation system control over PowerQUICC II The RXD TXD pins of the PowerQUICC...

Page 63: ...recepti ble of the type BERG CONANTM 91931 WXY21 with 1 mm pin pitch located on the bottom side of the PPC PMC 8260 DS1 module see Figure 10 JTAG Debug Connector on page 3 10 The following figure shows the pinout of the JTAG Debug mode connector Figure 11 JTAG Debug Connector Pinout Note The signals marked by an asterisk are COP signals ...

Page 64: ...On Board Connectors Indicators and Connectors 3 12 PPC PMC 8260 DS1 ...

Page 65: ...4 Firmware ...

Page 66: ......

Page 67: ...ea Execute application software from boot flash device Start primary booter to Load application software via PCI bus Program application software into the boot flash device Read from and write to all devices on the PPC PMC 8260 DS1 Obtain detailed results from the power on self test to evaluate error condi tions Controlling and monitoring the boot process Resources Used by the Firmware The PMC8260...

Page 68: ...tinue code execution there The following flow chart shows an overview of the steps performed by the firmware and also the steps which can be controlled by a driver Note The PMC8260 DS1 firmware does not display any banner or prompt on a terminal connected to the serial debug ports The firmware has no shell therefore it cannot accept commands from a terminal Only the front panel LEDs show the curre...

Page 69: ...Firmware Power Up Sequence PPC PMC 8260 DS1 4 5 Figure 12 Flowchart of the PPC PMC 8260 DS1 Firmware Power Up Sequence ...

Page 70: ...d start the previous two steps are omitted Skip POST The POST can be enabled disabled by setting the PSKIP bit in the PCR register Another way to influence the POST execution is to program the byte at flash offset 000400F116 see the Controlling Boot Process section on page 4 13 Set power up status PSR to POST Before the power on self test is started the value 1 is written into the power up status ...

Page 71: ...abled You can configure your ROM image to make the firmware change the System Protection Control register SYPCR settings and to disable the watchdog and the bus monitor This is done by programming the ROM image accordingly For further information see section SYPCR Register on page 4 9 Set power up status PSR to ROMEX Before the ROM image is executed the value 3 is written into the PSR This informa...

Page 72: ...ry to enable communication between PMC module and host when loading an image from PCI bus programming a ROM image into boot flash performing read write accesses to I O devices e g reading the boot flash contents or POST results Programming the boot image into boot flash not necessary if you want to load an image via PCI bus Reading and writing to I O devices Optional Reading POST results If you us...

Page 73: ...R register of the PowerQUICCC II at power up i e leaving the bus monitor and the software watchdog enabled A problem arises when the firmware detects and executes a ROM image which does not provide support for the software watchdog i e the watchdog is not triggered and the board is then reset To be able to install ROM images without watchdog support the firmware pro vides a mechanism to preset the...

Page 74: ...culated by adding IMG_SIZE bytes beginning at ROM image offset 10016 To perform the checksum test CSUM_ID must be set to C516 F016 1 SYPCR_WR If set to 0 the firmware will preset the SYPCR register of the PowerQUICC II with SYPCR_VAL see below before executing the ROM image Otherwise the SYPCR register is left in its reset state F116 1 POST_SKIP If set to 0 no POST will be executed by the firmware...

Page 75: ...REEN OFF Jump to ROM image offset 10816 address fe04 010816 If FLAGS SHADOW is 1 If FLAGS SMODE is 0 Copy block fe04 010016 fe20 000016 to RAM_ADRS else Copy block fe04 000016 fe20 000016 to RAM_ADRS If SYPCR_WR is 0 Write SYPCR_VAL to SYPCR register Set LEDs to GREEN OFF If RAM_EXEC is within the address range of the copied image Jump to RAM address RAM_EXEC else Jump to RAM_ADRS 10816 F416 4 SYP...

Page 76: ...Map on page 5 3 PowerSpan II The firmware uses mailbox registers 5 6 and 7 as control and status registers Fur thermore it programs the address translation of PCI base address register 2 so that it is mapped to the local DRAM Port Pin Configuration The firmware does not program the pin assignment registers for ports A C If you have purchased the Motorola Tornado 2 0 BSP for the PPC PMC 8260 DS1 or...

Page 77: ...is not possible to enable the software watchdog timer once it has been disabled except by resetting PPC PMC 8260 DS1 In any case the firmware will periodically trigger the software watchdog to prevent it from expiring r w 1 ROMSKIP 0 Firmware will look for a ROM image and execute it if one is found 1 Firmware will always execute primary booter and not look for ROM image r w 0 lsb PSKIP 0 Power on ...

Page 78: ... started host software must poll the PSR for a non zero value before accessing local resources on the 60x bus Otherwise the PMC module would hang because a non zero value means the power up procedure is not com pleted The following values and their mnemonics are defined 1 POST This value is set immediately before the power on self test is started 2 RDY This value is set after all initialization st...

Page 79: ...emory SDRAM 256 byte of main memory are used as control and sta tus register section CSR which is used for the communication protocol The CSR section is accessible both from the PCI bus via the default base translation register provided by the PCI bridge and the local PowerQUICC II The BST0 register of the PowerSpan II PCI bridge is configured to 4 MByte by hardware The primary booter maps this wi...

Page 80: ...ry booter and to report status codes back to the host Table 13 Primary Booter CSR Section Offset Size bytes Name and Description 016 4 SYNC A 4 byte ASCII string containing command and status codes for communication between host and PMC mod ule For a list of available commands see Table 14 Pri mary Booter Commands and Parameters page 4 18 416 4 ADRS Argument for SYNC This parameter is used for the...

Page 81: ...Y where y and y are the major and minor version numbers in the range of 0 to 9 MMM DD and YYYY are the firm ware s date code A016 1 CSPC Source destination address space must remain 0 A116 1 CWID Source Destination access width A216 2 Reserved A416 4 COFF Address of I O buffer offset relative to 01C0000016 in memory window A816 4 Reserved AC16 4 CADR Source or destination address B016 4 CSIZ Numbe...

Page 82: ...by CSPC beginning at flash device offset CADR COFF Address of I O buffer offset must be used relative to 01C0000016 CSIZ Number of bytes to be trans ferred CADR Destination address CSPC Destination address space must be 0 go Starts code execution at local memory address ADRS This command ter minates the primary booter i e all memory resources used by the primary booter can be overwritten For a cod...

Page 83: ...reted as offset relative to the beginning of the CSR section where a zero terminated error string is stored Written SYNC word Primary booter either does not support the command or some error prevents the read Copies bytes set by parameter CSIZ from memory window offset set by parameter COFF COFF Address of I O buffer offset must be used relative to 01C0000016 CWID Source access width must be 0 CAD...

Page 84: ...4 33 1 Configure PowerSpan II local interrupt INT5 as output Note Mailbox registers 5 6 and 7 are used by the firmware Using these PowerSpan II registers will cause firmware malfunction Therefore do not use the mailbox registers 5 6 and 7 2 Map one of PowerSpan II s mailbox or doorbell registers except mail box registers 5 6 and 7 to interrupt pin 5 3 Enable mailbox doorbell interrupt 4 Program ac...

Page 85: ...t OK or FAIL a firmware or hardware error occured and the PMC module has to be sent back to Motorola 10 Poll SYNC field at offset 0 of PCI memory window The following codes could be returned by the firmware OK Primary booter is ready for communication It is recommended to issue a PING command see Table 14 Primary Booter Commands and Parameters page 4 18 INIT Primary booter is currently initializin...

Page 86: ...he memory window into the COFF field in big endian data format 2 When accessing hardware devices with a specific port size it might be necessary to set the CWID field to 0 3 Write source destination address in the PPC PMC 8260 DS1 address space of read write operation into CADR field 4 Write number of bytes to be transferred into CSIZ field 5 For write operations store data to be written into I O ...

Page 87: ...COFF field in big endian data format to define I O buffer in area avail able as I O buffer 01C4000016 0200000016 4 Write programming offset into CADR field This offset is relative to the boot image area in the boot flash device not relative to the beginning of the boot flash device itself 5 Write number of bytes to be programmed into CSIZ field 6 Store data to be written into I O buffer 7 Start op...

Page 88: ...are watchdog timer to expire and reset the board Requirements POST results are obtained via the primary booter In order to evaluate the POST re sults your driver has to include at least the programming routines for Starting the pimary booter Program your software according to the description on page 4 33 Reading and writing Program your software according to the description on page 4 22 Reading PO...

Page 89: ... test results 24 Lucent T8105 test results 28 Reserved zero 2C Reserved zero Global Results The POST result code PRC is set and each bit represents one of the eight tests being executed plus an additional global POST failure bit 0 Table 16 POST Result and Status Bits Offset 0016 Bit Description 0 lsb POST Failure Set to 1 if at least one device failed the tests 1 3 Not used 4 Set to 1 if framer 1 ...

Page 90: ...onding bit as defined in table 16 POST Result and Status Bits on page 4 25 is set All other bits are cleared A val ue of zero indicates that the POST is either complete or a test has been completed and the next test is about to be started The TSR can be used to monitor the progress of the POST and to see what the last test was that has been executed in case of a fatal error Device Specific Results...

Page 91: ...0 i e shifted by four beginning with 1 for the first address 31 Fatal error during test execution Table 18 Synchronous SRAM Test Offset 0C16 Status Bit Description 0 lsb No device was detected at the expected address 1 The assembled SSRAM size as determined by probing is not supported 4 30 Memory pattern test failed The index of the long WORD which failed the test is stored in bits 4 31 i e shifte...

Page 92: ... the DMA0 source address register failed 5 Writing and verifying value 0 to the DMA0 source address register failed 31 Fatal error during test execution Table 20 Framer Tests Offset 14 2016 Status Bit Description 0 lsb No device was detected at the expected address 1 TYPE section in the ID register is not 0012 2 Data mismatch when accessing register at offset 0 3 Data mismatch when accessing regis...

Page 93: ...ss 1 Wrong device ID CSR register at offset FE16 2 Data mismatch when writing 5516 to the first byte of CAM Data Memory 1 3 Data mismatch when writing AA16 to the first byte of CAM Data Memory 1 31 Fatal error during test execution Firmware Obtaining Results from the Power On Self Test PPC PMC 8260 DS1 4 29 ...

Page 94: ...vironment Data Definitions some compatibility macros e g for vxWorks define UINT32 unsigned int define sleep s taskDelay s sysAuxClkRateGet Set this if host is big endian define BIG_ENDIAN_HOST define LLSB x x 0xff define LNLSB x x 8 0xff define LNMSB x x 16 0xff define LMSB x x 24 0xff ifdef BIG_ENDIAN_HOST define LONGSWAP x LLSB x 24 LNLSB x 16 LNMSB x 8 LMSB x define NOLONGSWAP x x else define ...

Page 95: ...ST 1 POST is executing define PMC8260_FW_PSR_RDY 2 Primary booter runs define PMC8260_FW_PSR_ROMEX 3 ROM image runs Primary Booter CSR section define PB_HDR_SYNC 0x00000000 Synchronization word define PB_HDR_ADRS 0x00000004 Adrs or error offset define PB_HDR_VERS 0x00000029 CSR Version define PB_HDR_CPU 0x00000040 Name of CPU define PB_HDR_VEND 0x00000050 FORCE COMPUTERS define PB_HDR_TARG 0x00000...

Page 96: ...ssert reset UINT32 dummy if reset Deassert PowerQuicc II reset by clearing mailbox 0 interrupt RWRITE PSPAN_ISR0 PSPAN_INT_MBOX0 return Set PowerQuicc II reset by asserting local interrupt 5 map mailbox 0 to LINT 5 RREAD PSPAN_IMR_MBOX dummy dummy dummy PSPAN_IMR_MBOX0 PSPAN_INT_INT5 PSPAN_IMR_MBOX0_S RWRITE PSPAN_IMR_MBOX dummy Enable mailbox 0 interrupt RREAD PSPAN_IER0 dummy RWRITE PSPAN_IER0 P...

Page 97: ...ontrol csrBase 1 Clear PSR and set INI and ROMSKIP in PCR RWRITE PMC8260_FW_PSR 0 RWRITE PMC8260_FW_PCR PMC8260_FW_PCR_INI PMC8260_FW_PCR_ROMSKIP Re start the module pmc8260_reset_control csrBase 0 Wait for firmware to come up printf waiting for firmware while done RREAD PMC8260_FW_PSR dummy switch dummy case 0 printf break case PMC8260_FW_PSR_POST printf POST break case PMC8260_FW_PSR_ROMEX print...

Page 98: ...us for seconds 0 seconds 5 seconds if strncmp PBSYNC INIT 4 printf if strncmp PBSYNC FAIL 4 printf Primary booter failure n return 0 if strncmp PBSYNC OK 4 printf OK n printf Board Name s n PBSTR PB_HDR_TARG printf Firmware Ver s n PBSTR PB_HDR_FVER return 1 sleep 1 printf timeout n return 0 ...

Page 99: ...cess int pmc8260_wait char memBase PCI window address int seconds 0 printf waiting while 1 if strncmp PBSYNC OK 4 printf OK n return 1 if strncmp PBSYNC FAIL 4 printf FAILURE n return 0 if strncmp PBSYNC BUSY 4 if seconds 2 printf command acknowledge timeout n return 0 printf sleep 1 if seconds 40 printf Still BUSY after 40 seconds n return 0 ...

Page 100: ...Buff memBase 0x100000 int remaining nbyte int size set copy arguments dfl size space and I O buffer offset PBWRITEB PB_HDR_CP_CSPC 0 PBWRITEB PB_HDR_CP_CWID 0 PBWRITEL PB_HDR_CP_COFF 0x100000 while remaining 0 size remaining 0x100000 0x100000 remaining PBWRITEL PB_HDR_CP_CADRL targAdrs PBWRITEL PB_HDR_CP_CSIZ size printf transferring d bytes from to target or flash adrs 0x x n size targAdrs if wri...

Page 101: ...erase char memBase PCI window address printf erasing ROM image strcpy PBSYNC eras if pmc8260_wait memBase return 0 return 1 Checking Alive State of Target Check alive status of Primary Booter Returns 0 on error 1 on success int pmc8260_ping char memBase PCI window address strcpy PBSYNC PING if pmc8260_wait memBase printf No answer n return 0 printf Target s 0x 08x is alive n PBSTR PB_HDR_TARG memB...

Page 102: ... PBSYNC go Reading POST Results Read and check POST results Returns 1 on success 0 on failure int pmc8260_post_get char memBase PCI window address UINT32 postArray POST result codes int i UINT32 chksum if pmc8260_rdwr memBase 0 postArray 0x30 0xf000b800 return 0 for i 0 i 12 i postArray i NOLONGSWAP postArray i chksum postArray 0 for i 2 i 12 i chksum postArray i if chksum postArray 1 postArray 0 ...

Page 103: ...postArray 7 printf Framer 4 s 0x 08x n postArray 0 1 7 pass fail postArray 8 printf T8105 s 0x 08x n postArray 0 1 8 pass fail postArray 9 printf PowerSpan s 0x 08x n postArray 0 1 9 pass fail postArray 4 printf DRAM s 0x 08x n postArray 0 1 10 pass fail postArray 2 printf SRAM s 0x 08x n postArray 0 1 11 pass fail postArray 3 return 1 ...

Page 104: ...Code Examples Firmware 4 40 PPC PMC 8260 DS1 ...

Page 105: ...5 Memory Map and Devices ...

Page 106: ......

Page 107: ... TMD link represented as a dotted line is only available on the H 110 F variant Tundra PowerSPAN II PCI Bridge 33 66 MHz SDRAM 64 Bit 64 MByte 66 MHz SSRAM 32 Bit 1 MByte 66 MHz Boot Flash 2 MByte Agere T8105 H 110 or SCbus Inter TDM Link Line 1 Line 2 Motorola MPC8260 300 MHz Framer PM4351 Framer PM4351 PCI Bus 32 64 bit 33 66MHz 60x Bus Local Bus Figure 14 Block Diagram ...

Page 108: ... PowerSPAN II Register 3000000016 3000100016 32 n a Decoded by PowerSPAN II 4 KByte space PB_REG_BADDR is one of four speciality proces sor bus slave images PowerQUICC II F000000016 F001FFFF16 32 n a 128 KByte register and internal RAM Internal Memory Map register IMMR power up option Internal Space Base ISB Framer 1 F004000016 F00401FF16 8 6 Framer 2 F004020016 F00403FF16 8 6 Framer 3 F004040016 ...

Page 109: ... PowerSPAN II framers T8105 and PowerQUICC II have interrupt capability The devices are connected to the PowerQUICC II according to the table below Table 23 Interrupt Inputs of the PowerQUICC II Device PowerQUICC II IRQ Input PowerSpan II INT0 IRQ1 PowerSpan II INT3 IRQ6 Framers 1 4 IRQ2 Timeslot Interchanger T8105 IRQ4 For further information refer to the MPC8260 PowerQUICC II User s Manual and t...

Page 110: ...e cause the short time out value could create an undesired machine check or reset in terrupt this can be programmed into the ROM image The firmware then sets the SYPCR register accordingly For further information refer to the ROM Image Configuration section on page 4 9 Communication Processor Module The CPM contains features that allow the PowerQUICC II to excel in a variety of applications target...

Page 111: ... Sheet Serial Interface with Time Slot Assigner and Multi Channel Controller Two Serial Interface SI blocks in the PowerQUICC II SI1 and SI2 can be pro grammed to handle eight TDM lines concurrently TDM channels on SI1 are referred to as TDMa1 TDMb1 TDMc1 TDMd1 TDM channels on SI2 are TDMa2 TDMb2 TDMc2 TDMd2 Each SI has the following features Connect to four independent TDM channels Each TDM can b...

Page 112: ...rQUICC II Memory Map and Devices 5 8 PPC PMC 8260 DS1 independent buffer descriptor BD tables For a detailed description of the TDM stream structure on the PPC PMC 8260 DS1 see the TDM Channel Configuration chapter ...

Page 113: ... arbiter Therefore if you want to change the access priorities of devices for ex ample you have to program the PowerQUICC II internal arbiter because the Pow erSPAN II 60x bus arbiter is not used E2 PROM Contents The PowerSPAN II s I2 C controller has a two wire interface Serial Data and Serial Clock lines which connects to a serial E2 PROM Certain registers of the PowerSPAN II can be programmed a...

Page 114: ...rSPAN II User Manual Note The settings printed in bold in the following table must not be modi fied Otherwise the proper function of the firmware delivered together with the PPC PMC 8260 DS1 cannot be guaranteed Table 25 PowerSPAN II Serial E2 PROM Contents Byte Offset Contents Affected PowerSPAN II Registers 0 0116 Defines short E2 PROM data format 1 4 0016 Reserved 5 0c16 P1_CSR BM Enable PCI bu...

Page 115: ...have been configured The data access is completed normally if the lockout state is left Note It must be ensured that the PCI lockout state is ended as soon as possible after power up Most PCI systems have a retry limit which may cause unpredictable results on the host if reached After ending the PCI lockout state it does not make sense to set it again for configuring the PowerSPAN II In its factor...

Page 116: ...must be programmed 1 Set bit BAR_EN to 1 to enable BAR in PCI configuration header 2 Set bit MODE to 0 to map BAR to PCI memory space or to 1 for PCI I O space 3 Set bit BS to define the size of translation image 4 Optional Set bit P1_BSTx PRFTCH to enable read prefetching P1_BSTx Configure the PCI base address by programming P1_BSTx This setting is usually performed by the PCI bus enumerator of t...

Page 117: ...memory space address D000000016 Read prefetching enabled 3 Set via configuration E2 PROM 3 P1_TI0_TADDR 000000FE16 60x bus base address 0000000016 Mx 1 Claim transactions from all masters P1_CSR 02B0000616 MS 1 Memory space enable BM 1 Bus master enable With these settings the PCI bus address range D000000016 to D040000016 corre sponds to the PPC PMC 8260 DS1 60x bus address range 0000000016 to 00...

Page 118: ...to allow PCI mastership to Power SPAN II This is usually done by the PCI enumerator The following programming example for 60x bus slave image 1 shows the register contents necessary to map 256 MBytes of 60x bus space beginning at address 2000000016 to PCI memory space address 0 Table 27 60x Bus Slave Image 0 Programming Example PowerSPAN II Register Register Contents Comment PB_SI0_BADDR 200000001...

Page 119: ...bridge Table 28 SDRAM Access on 60x Bus PowerPC Bus Device Size Width 60x bus Address Controlled by PowerQUICC II SDRAM 64 MByte 64 bit 0000000016 03FFFFFF16 programmable SDRAM machine SDRAM Machine Memory Controller The SDRAM interface supports back to back page mode A page remains open as long as back to back accesses that hit the page are generated on the bus The page is closed once the bus bec...

Page 120: ...nd burst write access parity generation and check is supported as a boot option Note The local bus does not burst when accessed from the PowerQUICC II core or from the external master PCI bridge PowerSPAN II Therefore re gions that are accessed across the 60x bridge to local bus must be marked as cache inhibited in the PowerQUICC II core MMU Otherwise these burst ac cesses will be terminated with ...

Page 121: ...ICC II pro cessor Accesses to the 60x bus and the local bus are possible at the same time From the address mapping the local bus is still mapped into the 32 bit 4 GByte 60x bus address space Table 30 SSRAM Address on 60x Bus Local Bus Device Size Width 60x Bus Local Bus Address CS Lines SSRAM 1 MByte 32 bit 1800000016 180FFFFF16 programmable CS2 CS3 CS4 CS5 ...

Page 122: ... is done via a bi directional data buffer not shown below which isolates these slow devices from the high speed SDRAM on the 60x bus Figure 15 I O Bus Boot Flash PROM The PPC PMC 8260 DS1 module provides a 2 MByte on board boot flash PROM which is 8 bit wide The access time of the flash PROM is 120 ns Table 31 Flash PROM Access on 60x Bus Device Size Width 60x Bus Address Controlled by Line Flash ...

Page 123: ...d from system according to carrier board s Installation Guide 3 Set SW1 2 to ON Note Switch SW1 2 must be in ON position during the whole procedure of reprogramming the boot flash from the PCI bus Be sure to put SW1 2 in OFF position after reprogramming the boot flash otherwise the PPC PMC 8260 DS1 will not power up 4 Install carrier board into system according to carrier board s Installation Guid...

Page 124: ... 64 bit port size devices on the 60x bus side high order 60x addresses connected to an external multiplexer are used to access the 8 bit boot flash device See the following figure for a symbolic block diagram of the byte address generation Figure 16 Byte Address Generation for Flash Programming from PCI Bus via PowerSPAN II Memory Map when PowerQUICC II is in Reset To accommodate the flash program...

Page 125: ... in Reset 60x Address A 0 31 60x Address 7 8 9 Flash Byte Address 2 1 0 Size MByte Addressable Flash Byte Addresses xx000000 xx3FFFFF 000 000 4 xxxxxxx0 xxxxxxx8 xx400000 xx7FFFFF 001 001 4 xxxxxxx1 xxxxxxx9 xx800000 xxBFFFFF 010 010 4 xxxxxxx2 xxxxxxxA xxC00000 xxFFFFFF 011 011 4 xxxxxxx3 xxxxxxxB x1000000 x13FFFFF 100 100 4 xxxxxxx4 xxxxxxxC x1400000 x17FFFFF 101 101 4 xxxxxxx5 xxxxxxxD x1800000...

Page 126: ...nnected to PQ2_D 0 7 the dummy write access must be addressed to byte address 016 Note After any reset the LED register see the LED Control Register sec tion on page 5 23 also gets reset resulting in the two front panel LEDs light ing up yellow Agere Ambassador T8105 The H 110 bus SCbus controller Agere Ambassador T8105 provides a complete interface between the H 110 backplane bus and four E1 T1 J...

Page 127: ... The E1 or T1 line interface transmit signal strongly depends on the cable length and the resulting signal attenuation When using a long ca ble the pulse must be stronger than when using short cables The pulse shape is programmable via framer registers and can easily be adapted to the user s application For a detailed description refer to the PMC Sierra PM4351 data sheets The E1 T1 J1 signal lines...

Page 128: ...r is also reset resulting in the front panel LEDs lighting up yellow Table 37 LED Control Register Address F00A000016 Bit Signal Description Access 7 LSB L1 red LED 1 lights red 0 LED on default 1 LED off w 6 L1 green LED 1 lights green 0 LED on default 1 LED off w 5 L2 red LED 2 lights red 0 LED on default 1 LED off w 4 L2 green LED 2 lights green 0 LED on default 1 LED off w 3 L3 red L3 lights r...

Page 129: ...ices I O Bus PPC PMC 8260 DS1 5 25 0 MSB L4 green L4 lights green1 0 LED on default 1 LED off w 1 The settings currently have no effect Table 37 LED Control Register cont Address F00A000016 Bit Signal Description Access ...

Page 130: ...ication software hang program the PowerSPAN II INT 5 signal from the PCI bus as follows 1 On carrier board configure interrupt INT5 as output Note Mailbox registers 5 6 and 7 are used by the firmware Using these PowerSpan II registers will cause firmware malfunction Therefore do not use the mailbox registers 5 6 and 7 2 Set up one of PowerSpan II s mailbox registers except mailbox registers 5 6 an...

Page 131: ... asserted PowerQUICC II in normal operating mode Program a reset of the I O devices as follows 1 Configure interrupt INT4 as output Note Mailbox registers 5 6 and 7 are used by the firmware Using these PowerSpan II registers will cause firmware malfunction Therefore do not use the mailbox registers 5 6 and 7 2 Set up one of PowerSpan II s mailbox registers except mailbox registers 5 6 and 7 to tri...

Page 132: ...Resetting the Devices Memory Map and Devices 5 28 PPC PMC 8260 DS1 ...

Page 133: ...6 TDM Channel Configuration ...

Page 134: ......

Page 135: ...you do not need this information because the settings are already implemented in the software The following information is given Bit clock and frame pulse pins used on the PPC PMC 8260 DS1 necessary to program a synchronous network How the Time Division Multiplex TDM channels of the PowerQUICC II are connected to the framers and the H 110 SCbus via the T8105 timeslot inter changer to enable timesl...

Page 136: ...T8105 XTALIN XTALOUT pins CTBus network reference clocks CT_NETREF_1 and CT_NETREF_2 see Figure 17 Local TDM Clocking Structure on page 6 5 To use one of these clocks select one of the L_REF input pins the quarz oscillator input pin or the CT_NETREF_x input pins inside the T8105 switch via T8105 reg isters The selected clocks are then distributed via frame pulse clock line L_SC_1 and bit clock lin...

Page 137: ...PPC PMC 8260 DS1 6 5 CT_C8_A CT_FRAME_A CT_C8_B and CT_FRAME_B as output and set FET_CTRL_A and FET_CTRL_B to 0 For information on the T8105 and the registers needed for programming refer to the T8105 data sheets Figure 17 Local TDM Clocking Structure ...

Page 138: ... L_SC_1 and bit clock line TCLK_OUT and a clock driver to the clock lines of the framers BTCLK BTFP and the PowerQUICC II L1RCLK and L1RSYNC Figure 17 Local TDM Clocking Structure on page 6 5 shows these clock lines The T8105 general purpose I O pins FET_CTRL_A and FET_CTRL_B must be configured to activate the 33 Ohm series resistors of line A and B This is accom plished by setting the bits FET_CT...

Page 139: ... supporting 32 timeslots The framers support 24 timeslots if configured for T1 J1 or 32 timeslots if configured for E1 To be able to build your specific network each of the mentioned timeslots can be switched between Local TDM channels between the PowerQUICC II and the framers H 110 SCbus TDM channels Local TDM channels and H 110 SCbus TDM channels This means that any local timeslot can be switche...

Page 140: ...e framers backplane receive transmit PCM BRPCM and BTPCM data lines and which T8105 local TDM channel data lines are connected to the PowerQUICC II SI1 and SI2 TDM lines If for example a timeslot is to be routed from framer 2 to PowerQUICC II TDM channel A2 it has to be routed between LDI_1 and LDO_8 in the T8105 Note The connection of data lines of the inter TDM link is shown in a separate figure...

Page 141: ...he H 110 bus allows to connect only PMC slot 2 to the H 110 backplane bus connector P4 Therefore PPC PMC 8260 DS1 modules mounted in PMC slot 1 of the reference CompactPCI carrier boards do not have a physical H 110 bus connection To allow sharing and exchanging TDM streams between the two PMC slots the Motorola reference CompactPCI carrier boards CPCI 6750 Rev 2 x and MFIO 120 implement an on boa...

Page 142: ...1 of the PMC 8260 DS1 H110 in the lower PMC slot 1 The same applies to the clock out put and the frame pulse output signals In the other direction from the lower PMC slot 1 to the upper PMC slot 2 four ad ditional TDM output streams and two clock signals are cross routed via the carrier board to the four TDM input streams and two clock inputs of the upper PMC slot 2 Note The inter TDM link is only...

Page 143: ...II port registers For further infor mation see the MPC8260 PowerQUICC II User s Manual Note Since only PowerQUICC II receive clock pins are connected to the clock driver PowerQUICC II TDM interfaces have to be configured to use common clock pins for RX TX CLK and SYNC These common clocks are fed into RXCLK and RSYNC Table 38 Used Port Pins of SI1 PowerQUICC II Port Pin Used Function PA08 L1RXD_A1 ...

Page 144: ...9 L1RCLK_A2 PB04 L1RSYNC_A2 PB30 L1RXD_B2 PB31 L1TXD_B2 PC17 L1RCLK_B2 PB29 L1RSYNC_B2 PB26 L1RXD_C2 PB27 L1TXD_C2 PB17 L1RCLK_C2 PB24 L1RSYNC_C2 PB22 L1RXD_D2 PB23 L1TXD_D2 PA03 L1RCLK_D2 PB20 L1RSYNC_D2 PowerQUICC II Port Functions on PPC PMC 8260 DS1 TDM Channel Configuration 6 12 PPC PMC 8260 DS1 ...

Page 145: ...A Troubleshooting ...

Page 146: ......

Page 147: ...n ROM image area does not start LEDs switch to yellow yellow after green off A software reset occured while executing the ROM image Configure ROM image so that firmware dis ables the watchdog before executing it see SYPCR Register page 4 9 Add software watchdog support to applica tion in ROM image area After Power Up LEDs remain yellow yellow after power up Wrong switch settings Verify switch sett...

Page 148: ...A 4 PPC PMC 8260 DS1 ...

Page 149: ...rface 3 PowerQUICC II frequency 3 PowerQUICC II Port Functions 11 PowerQUICC II version 3 PowerQUICCII serial I O channel usage 4 PowerSpan 3 Primary booter 15 Protocol software packages 3 R Resources used by primary booter 16 ROM image configuration section 10 ROM image execution 9 13 S SCbus specification 5 SDRAM performance 15 Serial EEPROM Contents 10 Skipping POST 13 SSRAM performance 16 Star...

Page 150: ...I 2 PPC PMC 8260 DS1 ...