Motorola Internal Use
11
V2288 – Circuit Description
6)
When high
CHGR_SW
will limit the CLA or EIHF current output to 400mA, when
low
MANTEST_AD
the current output is limited to 900mA. The AC charger output
a current of approximately 350mA.
7)
When the batteries are discharged and we turn the phone on, for the first second, full
rate charge is delivered, (this is due to the LX signal for V_BOOST being unstable
and therefore creating a power surge). This enables the phone to consume most of the
current from the charger but at the same time trickle charge the batteries up to their
usable voltage level. This is achieved by setting
ENABLE
'high': from Whitecap Pin
L7 to COVIC
Pin 5
and
TRLK_SET
'low' (Whitecap
Pin K4
to COVIC
Pin 2
). The
result of this is that the signal
DRV
, COVIC
Pin 1
opens or closes the ‘gate’ of
Q960
(very similar to the
CHARGC
function of other GCAP II products). The charge is
then fed through
CR960
and out to
dual-FET Q691
to charge the battery.
8)
The circuit function describing when the batteries are in the usable range and normal
full rate charging is enabled is as above, however the extra current now charges the
batteries and the support voltage for the phone is taken directly from the batteries.
9)
For High Rate trickle charging, again the operation is as above but
TRKL_SET
is set
‘high’ and
ENABLE
set ‘low’.
10)
For Low rate Trickle charging
TRKL_SET
is set ‘low’ and
ENABLE
is set ‘low’
11)
I Sense COVIC Pin 7 is used as a control for the charging DRV signal
12)
The Over Voltage protection part of the circuit works in the following way:
13)
The normal operating range of the batteries is between 3V through to 4.5V and an
over voltage condition would be classed at >5.1V. If a transient above this occurred
then this would be sensed by the current Sense resistor R960, and fed back into the
COVIC on Pin 7. This would drive ENABLE ‘low’, enabling Trickle charge mode
and reducing the current to the batteries to approximately 40mA.
14)
If the transient is >6.1V then all charging stops. The over voltage comparator within
the COVIC has hysterisis built in and the capacitors will begin to discharge until the
voltage level is <5.1V at this point
I_SENSE
is reviewed again if still > 5.1V the unit
begins to trickle charge.
15)
Instrumental in both these operations being carried out successfully is a 10
µ
F
capacitor C970 (Situated near
V_BOOST
circuitry). As the transient occurs this
capacitor charges up, and reduces the voltage rise to the COVIC circuit, therefore
giving the COVIC more time to operate.
Logic: Deep Sleep Mode
1)
Deep sleep mode is there to provide a facility to save battery life by intermittently
shutting off part of the PCB. This is achieved in the following way. The signal
STBY_DL
is generated from Whitecap
Pin F1
, through a standby delay circuit
CR912
and
U906
and onto
Q834
and
Q912
. This has the effect respectively of:
2)
Grounding
VREF
which makes MAGIC inoperable
3)
Grounding
V2
This switches off MAGIC, Front END IC and inhibits the Transmit
path through
RF_V2
4)
The shutdown is only for a fraction of a second and during that time the GCAP Clock
supports the logic side of the unit. The GCAP clock is generated by
Y900
, which
