AWARD
®
BIOS Setup
3-13
RAS# to CAS# Delay
When DRAM is refreshed, both rows and columns are addressed
separately. This setup item allows you to determine the timing of the
transition from RAS (row address strobe) to CAS (column address strobe).
The less the clock cycles, the faster the DRAM performance. Setting
options:
3
,
2
.
RAS# Precharge
This item controls the number of cycles for Row Address Strobe (RAS) to
be allowed to precharge. If insufficient time is allowed for the RAS to
accumulate its charge before DRAM refresh, refresh may be incomplete
and DRAM may fail to retain data. This item applies only when synchro-
nous DRAM is installed in the system. The settings are:
2
and
3
.
DRAM Frequency
Use this item to configure the clock frequency of the installed SDRAM. Set-
tings are:
Auto, DDR200, DDR266
.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delayed
transactions cycles so that transactions to and from the ISA bus are buffered
and PCI bus can perform other transactions while the ISA transaction is
underway. Select
Enabled
to support compliance with PCI specification ver-
sion 2.1. The settings are:
Enabled
and
Disabled
.
AGP Aperture Size (MB)
This setting controls just how much system RAM can be allocated to AGP for
video purposes. The aperture is a portion of the PCI memory address range
dedicated to graphics memory address space. Host cycles that hit the aperture
range are forwarded to the AGP without any translation. The option allows the
selection of an aperture size of
4, 8, 16, 32, 64, 128, and 256
(MB)
.
On-Chip Video Window Size
This setting controls just how much system RAM can be allocated to onboard
video controller for video purposes. The display cache window is a portion of
the PCI memory address range dedicated to graphics memory address space.
Host cycles that hit the aperture range are forwarded to the onboard video
device without any translation. Setting options:
Disabled, 64MB
,
128MB
.
