3-10
M S-7242 M ainboard
Advanced Chipset Features
DRAM Timing
Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect) EEPROM
on the DRAM module. Setting to [Auto] enables DRAM timing to be determined auto-
matically by BIOS based on the configurations on the SPD. Selecting [Manual] allows
users to configure the following fields manually.
CAS# Latency (Tcl)
This controls the CAS latency, which determines the timing delay (in clock
cycles) before SDRAM starts a read command after receiving it. Smaller clocks
increase system performance while bigger clocks provide more stable system
performance.
RAS# Precharge Time (Trp)
W hen the
DRAM Timing
is set to [Manual], this field is adjustable. This setting
controls the number of cycles for Row Address Strobe (RAS) to be allowed to
precharge. If insufficient time is allowed for the RAS to accumulate its charge
before DRAM refresh, refresh may be incomplete and DRAM may fail to retain
data. This item applies only when synchronous DRAM is installed in the system.
RAS# to CAS# Delay (Trcd)
This field lets you insert a timing delay between the CAS and RAS strobe
signals, used when DRAM is written to, read from, or refreshed. [Disabled]
gives faster performance; [Enabled] gives more stable performance.
