3-21
BIOS Setup
Advance DRAM Configuration
Press <Enter> to enter the sub-menu and the following screen appears:
Configure DRAM Timing by SPD
Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect)
EEPROM on the DRAM module. Setting to [Auto By SPD] enables DRAM timings
and the following related items to be determined by BIOS based on the configu-
rations on the SPD. Selecting [Manual] allows users to configure the DRAM
timings and the following related items manually.
DRAM CAS# Latency
This controls the CAS latency, which determines the timing delay (in clock cycles)
before SDRAM starts a read command after receiving it.
DRAM RAS# to CAS# Delay
This field allows you to set the number of cycles for a timing delay between the
CAS and RAS strobe signals, used when DRAM is written to, read from or
refreshed. Fast speed offers faster performance while slow speed offers
more stable performance.
DRAM RAS# Precharge
This item controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If insufficient time is allowed for the RAS to accumulate its
charge before DRAM refresh, refresh may be incomplete and DRAM may fail to
retain data. This item applies only when synchronous DRAM is installed in the
system.
DRAM RAS# Activate to Prechar
This setting determines the time RAS takes to read from and write to a memorycell.
Setting options: [8~15 DRAM Clocks].
Summary of Contents for MS-7357 (V1.X)
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