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CPu Core Control
this item is used to control number of CPu cores. When set to [auto], the CPu will
operate under the default number of cores. When set to [manual], you will be able
to enable/disable the specific CPu core.
Core / 2/ 3/ 4
these items are used to enable/disable the core / 2/ 3/ 4.
oC Genie Lite
Setting this item to [enabled] allows the system to detect the maximum FSB clock
and to overclock automatically. if overclocking fails to run, you can try the lower
FSB clock for overclocking successfully.
advance dRam Configuration
Press <enter> to enter the submenu.
dRam timing mode
this field has the capacity to automatically detect the dRam timing. if you set
this field to [dCt 0], [dCt ] or [Both], some fields will appear and selectable.
dCt 0 controls channel a and dCt controls channel B.
dRam drive Strength
this item allows you to control the memory data bus’ signal strength. increasing
the drive strength of the memory bus can increase stability during overclock-
ing.
dRam advance Control
this field has the capacity to automatically detect the advanced dRam timing.
if you set this field to [dCt 0], [dCt ] or [auto], some fields will appear and
selectable.
t/2t memory timing
When the dRam timing mode is set to [manual], the field is adjustable. this
field controls the command rate. Selecting [t] makes dRam signal controller
to run at clock cycle rate. Selecting [2t] makes dRam signal controller run
at 2 clock cycles rate.
dCt unganged mode
this feature is used to integrate two 64-bit dCts into a 28-bit interface.
Bank interleaving
Bank interleaving is an important parameter for improving overclocking capabil-
ity of memory. it allows system to access multiple banks simultaneously.
Power down enable
this is a memory power-saving technology. When the system does not access
memory over a period of time, it will automatically reduce the memory power
supply.
memClk tristate C3/atLVid
this setting allows you to enable/disable the memClk tristating during C3 and
atLVid.
