© National Instruments
|
7-29
In Legacy Mode, the counter operation requires two counters and does not use the embedded
counter. For example, to generate four pulses on Counter 0, Counter 0 generates the pulse train,
which is gated by the paired second counter. The paired counter, Counter 1, generates a pulse of
desired width.
Note
Counter 0 is always paired with Counter 1. Counter 2 is always paired with
Counter 3.
The routing is done internally. Figure 7-30 shows an example finite pulse train timing diagram.
Figure 7-30.
Finite Pulse Train Timing in Legacy Mode
Retriggerable Pulse or Pulse Train Generation
The counter can output a single pulse or multiple pulses in response to each pulse on a hardware
Start Trigger signal. The generated pulses appear on the Counter
n
Internal Output signal of the
counter.
You can route the Start Trigger signal to the Gate input of the counter. You can specify a delay
from the Start Trigger to the beginning of each pulse. You can also specify the pulse width. The
delay and pulse width are measured in terms of a number of active edges of the Source input.
The initial delay can be applied to only the first trigger or to all triggers using the
CO.EnableInitalDelayOnRetrigger property. The default for a single pulse is True, while the
default for finite pulse trains is False.
The counter ignores the Gate input while a pulse generation is in progress. After the pulse
generation is finished, the counter waits for another Start Trigger signal to begin another pulse
generation. For retriggered pulse generation, pause triggers are not allowed since the pause
trigger also uses the gate input.
Co
u
nter 1
(P
a
ired Co
u
nter)
Co
u
nter 0
Gener
a
tion
Complete
Summary of Contents for 6368
Page 1: ...PXIe 6368...
