National Instruments 6509, Programmer'S Manual

Page 1: ...DAQ Static DIO Register Level Programmer Manual for NI 6509 651x 6520 6521 and 6528 Devices Static DIO Register Level Programmer Manual November 2005 371580A 01...

Page 2: ...2 2970 Korea 82 02 3451 3400 Lebanon 961 0 1 33 28 28 Malaysia 1800 887710 Mexico 01 800 010 0793 Netherlands 31 0 348 433 466 New Zealand 0800 553 322 Norway 47 0 66 90 76 60 Poland 48 22 3390150 Por...

Page 3: ...or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be rep...

Page 4: ...Configuration Registers 2 6 RiseEdgeEnable N 2 6 Falling Edge Sensitivity Configuration Registers 2 7 FallEdgeEnable N 2 7 Filter Enable Registers 2 8 FilterEnable N 2 8 Watchdog Timers High Impedanc...

Page 5: ...23 RTSI Pulse when Edge Detected 2 24 RTSI Pulse when Watchdog Timer Expires 2 25 RTSI Trigger for Watchdog Timer 2 26 RTSI Edge Detection Configuration Register 2 27 Chapter 3 Programming Programming...

Page 6: ...rogramming using NI DAQ driver software or application development software such as LabVIEW Measurement Studio for Visual Studio NET or LabWindows CVI you do not need to read this manual Note While it...

Page 7: ...these guides when you are making your connections The terminal block and cable assembly installation guides or accessory board user manuals explain how to physically connect the relevant pieces of you...

Page 8: ...tion to a key concept Italic text also denotes text that is a placeholder for a word or value that you must supply monospace Text in this font denotes sections of code programming examples and syntax...

Page 9: ...Refer to Table 1 1 for more information on port directions for the NI 651x devices The NI 6520 6521 devices contain five Form A single pole single throw SPST non latching relay outputs three Form C s...

Page 10: ...s Initialize the PCI interface before using the general operation registers Read the ID Register one of the general operation registers to verify the PCI interface is initialized properly For more inf...

Page 11: ...O I O I O I O I O I O PXI 6509 I O I O I O I O I O I O I O I O I O I O I O I O PCI 6510 I I I I PCI 6511 I I I I I I I I PXI 6511 I I I I I I I I PCI 6512 O O O O O O O O PXI 6512 O O O O O O O O PCI...

Page 12: ...he device base address Base Address Register 1 the size of the register in bits and the type of register read only write only or read and write Registers are grouped in the table by function A bit by...

Page 13: ...chdog Timer High or Low WatchdogHighLow N 0x48 0xN0 Read write 8 bit RTSI Enable RTSI_En N 0x49 0xN0 Read write 8 bit Note N is the port number in hexidecimal Ports can range from 0 to 11 0x0 to 0xB d...

Page 14: ...bit register with four 8 bit reads may create invalid data Table 2 3 NI 6509 651x 6520 6521 6528 Register Address Map Watchdog Timer Registers Register Name Offset Hex Type Size Watchdog Timer Softwar...

Page 15: ...t N where N is the port number in hexidecimal Note Ports can range from 0 to 11 0x0 to 0xB depending on your device For each port you must add an additional offset equal to 0x10 time the port number i...

Page 16: ...11 0x0 to 0xB depending on your device For each port you must add an additional offset equal to 0x10 time the port number in hex Address Offset 0x41 0x N 0 Type Read write Size 8 bit Bit Map Bit Name...

Page 17: ...ges where N is the port number in hexidecimal Note Ports can range from 0 to 11 0x0 to 0xB depending on your device For each port you must add an additional offset equal to 0x10 time the port number i...

Page 18: ...for falling edges where N is the port number in hexidecimal Note Ports can range from 0 to 11 0x0 to 0xB depending on your device For each port you must add an additional offset equal to 0x10 time the...

Page 19: ...interval Note Ports can range from 0 to 11 0x0 to 0xB depending on your device For each port you must add an additional offset equal to 0x10 time the port number in hex Address Offset 0x44 0x N 0 Type...

Page 20: ...11 0x0 to 0xB depending on your device For each port you must add an additional offset equal to 0x10 time the port number in hex Address Offset 0x46 0x N 0 Type Read write Size 8 bit Bit Map Bit Name...

Page 21: ...output or bidirectional ports Note Ports can range from 0 to 11 0x0 to 0xB depending on your device For each port you must add an additional offset equal to 0x10 time the port number in hex Address Of...

Page 22: ...gHighLow N is only valid for fixed output and bidirectional ports Note Ports can range from 0 to 11 0x0 to 0xB depending on your device For each port you must add an additional offset equal to 0x10 ti...

Page 23: ...Map Bit Name Description 7 0 RTSI_En 7 0 Write a 1 to any bit to enable RTSI routing to the corresponding port bit RTSI can only be enabled on two ports The second port can only have one bit the leas...

Page 24: ...dentifying code for the board Use this register to confirm that you are successfully reading from your device Address Offset 0x00 Type Read Size 8 bit Bit Map Bit Name Description 7 0 ID 7 0 Contains...

Page 25: ...RstWDT Set this bit to 1 periodically less than the minimum watchdog timer expiration interval to indicate that the application is running as expected 4 ClrWDTExp Set this bit to 1 to clear the effect...

Page 26: ...has been a falling edge that could cause an interrupt if falling edge interrupts are enabled 3 Rising Edge Status A 1 indicates that there has been a rising edge that could cause an interrupt if risin...

Page 27: ...xp IntEnable Enable interrupt on watchdog timer expiration 4 Falling Edge IntEnable Enable interrupt on falling edge detection 3 Rising Edge IntEnable Enable interrupt on rising edge detection 2 Maste...

Page 28: ...et 0x04 Type Read Size 32 bit Bit Map Bit Name Description 31 0 Rev 31 0 Contains the revision of your device 31 30 29 28 27 26 25 24 Rev 31 Rev 30 Rev 29 Rev 28 Rev 27 Rev 26 Rev 25 Rev 24 23 22 21 2...

Page 29: ...t Map Bit Name Description 31 20 Reserved Write only zeros to these bits 19 0 FI 19 0 Filter interval bits 19 and down to 0 in increments of 200 ns For more information on digital filtering registers...

Page 30: ...t 1 Read only Size 8 bit Bit Map Bit Name Description 7 2 Reserved Write only zeros to these bits 1 SystemClockStatus Bit 1 indicates which clock is currently being used as the system clock SClk A 0 i...

Page 31: ...cified expiration states when the watchdog timer expires Address Offset 0x15 Type Read write Size 8 bit Bit Map Bit Name Description 7 1 Reserved Write only zeros to these bits 0 WDTSwToEn Set this bi...

Page 32: ...whether or not the device is currently in the expiration state Address Offset 0x17 Type Read Size 8 bit Bit Map Bit Name Description 7 1 Reserved Disregard these bits 0 WDTExpStat A 0 indicates the de...

Page 33: ...WDT_TI 31 0 Set these bits to specify the amount of time in increments of 100 ns the device waits before going to the expiration state 31 30 29 28 27 26 25 24 WDT_TI 31 WDT_TI 30 WDT_TI 29 WDT_TI 28...

Page 34: ...RTSI IR 8 0 If a bit is 1 in this register it should not be 1 in any other RTSI register Write a 1 to a bit to make that RTSI line drive the value of the corresponding pin of the RTSI enabled input po...

Page 35: ...escription 15 9 Reserved Write only zeros to these bits 8 0 RTSI PED 8 0 If a bit is 1 in this register it should not be 1 in any other RTSI register Write a 1 to a bit to make that RTSI line drive th...

Page 36: ...Name Description 15 9 Reserved Write only zeros to these bits 8 0 RTSI PWE 8 0 If a bit is 1 in this register it should not be 1 in any other RTSI register Write a 1 to a bit to make that RTSI line p...

Page 37: ...ave to be 1 for the port to allow the watchdog timer to expire Write a 1 to this register to allow the watchdog timer to expire on a rising falling RTSI line RTSI Trig 8 corresponds to the PXI Star Tr...

Page 38: ...s edge detectors pulses as short as 10 ns can trigger the edge detection in compliance with PXI specifications At power up asynchronous edge detection is selected by default Address Offset 0x16 Type R...

Page 39: ...ng Linux and Mac OS X It also includes an OS generic bus interface you can use to support additional operating systems To download the NI Measurement Hardware DDK and NI 6509 651x 6520 6521 6528 examp...

Page 40: ...guration space for the National Instruments vendor ID 0x1093 and one of the device IDs listed in Table 3 1 1 You can obtain more information on PCI BIOS calls from the PCI SIG online at www pcisig com...

Page 41: ...the next and last instructions to initialize the device All values in this example are 32 bits Use the following pseudocode to re map the PCI MITE to memory address 0xD0000 and the device to memory a...

Page 42: ...rite the address to which you want to re map the device other than the PCI MITE to PCI configuration space offset 0x14 BAR1 Create the window data value by masking the new device address window data v...

Page 43: ...Instruments Application Engineers make sure every question receives an answer For information about other technical support options in your area visit ni com services or contact your local office at...

Page 44: ...com calibration If you searched ni com and could not find the answers you need contact your local office or NI corporate headquarters Phone numbers for our worldwide offices are listed at the front of...

Page 45: ...ication Specific Integrated Circuit a proprietary semiconductor component designed and manufactured to perform a set of specific functions for a specific application C CompactPCI refers to the core sp...

Page 46: ...uity to eliminate high potential differences and transients optocoupler a device that transfers electrical signals by utilizing light waves to provide coupling with electrical isolation between input...

Page 47: ...aration of Conformity NI resources A 1 diagnostic tools NI resources A 1 DN bits IO Port Data register 2 4 drivers NI resources A 1 E examples NI resources A 1 F FEE N bits Falling Edge Sensitivity Co...

Page 48: ...ramming examples NI resources A 1 R recurring port registers Falling Edge Sensitivity Configuration registers 2 7 Filter Enable registers 2 8 IO Port Data 2 4 IO Select registers 2 5 Rising Edge Sensi...

Page 49: ..._En N bits RTSI Enable registers 2 12 S software NI resources A 1 T technical support resources A 1 training and certification NI resources A 1 troubleshooting NI resources A 1 W WDT_En bits Watchdog...