Configuration and Installation
Chapter 2
SCXI-1100 User Manual
2-26
© National Instruments Corporation
Timing Requirements and Communication Protocol
Timing Signal
The data acquisition timing signal is SCANCLK.
SCANCLK increments MUXCOUNTER on its rising edge. Figure 2-9 shows the timing
requirements of the SCANCLK signal that ensure that SCANCLK is properly transmitted over
TRIG0.
T
low
T
high
SCANCLK
T
low
Time low before rising edge
400 nsec minimum
T
high
Time high before falling edge
250 nsec minimum
Figure 2-9. SCANCLK Timing Requirements
For settling time specifications, refer to Appendix A, Specifications.
Communication Signals
This section describes the methods for communicating on the Serial Peripheral Interface (SPI)
bus and their timing requirements. The communication signals are SERDATIN, DAQD*/A,
SLOT0SEL*, SERDATOUT, and SERCLK. Furthermore, Slot 0 produces SS* according to
data acquisition board programming, so this section also describes SS* timing relationships. For
more information on the Slot 0 Slot-Select Register, consult Chapter 4, Register Descriptions.
The data acquisition board writes a slot-select number to Slot 0 to determine to which slot the
board will talk. In the case of an SCXI-1001 chassis, this write also determines to which chassis
the data acquisition board will talk. Writing a slot-select number also programs the Slot 0
hardscan circuitry. See Chapter 5, Programming, for information on programming the Slot 0
hardscan circuitry.
Use the following procedure to select a slot in a particular chassis. Figure 2-10 illustrates the
timing of this procedure with the example case of selecting Slot 11 in Chassis 9. Notice that the
factory-default chassis address for the SCXI-1000 is address 0. For information on changing the
address of your chassis, consult the SCXI-1000/1001 User Manual. An SCXI-1000 chassis
responds to any chassis number.
