Chapter 8
AutoCode Sim Cdelay Scheduler
©
National Instruments Corporation
8-9
Sim Cdelay Scheduler
As stated at the outset, the goal of this project was to develop a new
AutoCode scheduler, runnable on real-time targets, which mimics the
behavior of Sim with Cdelay (
actiming
off). Sim with Cdelay differs
from Sim with
actiming
in several key ways, including scheduler
pipeline, task output posting policies, enable policies, and retriggering
behavior for triggered tasks.
Notice that, unlike the stock AutoCode scheduler, Sim with Cdelay’s
scheduler posts outputs twice per invocation. Outputs of tasks that are ATR
are posted exclusively during the first output posting stage, while tasks that
are ANC have their outputs posted during the second output stage. Between
the two output postings stages is the queue tasks phase, which queues up
those tasks that are ready to start executing that cycle. Because all the ATR
tasks post their outputs before this stage, it is clear that under this new
pipeline configuration, any task enabled or triggered by an ATR task will
be queued for execution during the same cycle its input goes high.
In addition to the altered scheduler pipeline, Sim with Cdelay also entails
new output posting options for certain tasks. In fact, the output posting
policy of all periodic blocks (both free-running and enabled) goes from
ANC (Sim with
actiming
) to ATR (Sim with Cdelay). For free-running
tasks, ANC versus ATR does not really make a difference—it is just a
paradigm shift. However, for enabled periodic tasks, the shift from ANC to
ATR leads to a very tangible reduction in output posting latency.
One of the remaining changes brought by Sim with Cdelay is the move
from a
sync immediate on enable policy (default AutoCode scheduler), in
which the enabled task is queued for execution on the first minor cycle its
enable input is seen to go high, to a global timeline enable policy. Unlike
the previous two modifications, this switch has a deleterious effect on
output latency. The enable policy only matters in a given model if the
scheduler minor cycle differs from the major cycle of one of the tasks; thus,
it has no effect on the model presented at the beginning of this chapter.
The other change entailed by Sim with Cdelay affects how retriggering is
handled for ATR triggered tasks if the computation has concluded but the
task has not yet posted its outputs. The default scheduler queues the trigger
(at most one), releasing it (and allowing the system to be triggered again)
only when its outputs are finally posted. Conversely, with Sim with Cdelay,
the trigger is immediately acted on, even though the outputs have not been
posted. Notice that this has the unfortunate consequence that a sequence of
