Chapter 8
AutoCode Sim Cdelay Scheduler
8-8
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Now the inherent problem in the standard scheduler is clear. From launch
to output posting, you suffer a two-cycle delay for triggered tasks, and a
three-cycle delay for enabled tasks, instead of the standard unit cycle delay
present on real-time hardware for free-running periodic tasks. Your goal
will be to reduce both of these latencies to single-cycle delays. The
scheduler pipeline stages in the Sim Cdelay AutoCode scheduler are shown
in Figure 8-4.
Figure 8-4.
Scheduler Pipeline Stages in the Sim Cdelay AutoCode Scheduler
Reset DataStore
Writers to Low
Priority
Read External
Inputs
Queue Tasks
Identify Outputs
to Post
Post Outputs
Write DataStores
from External
Inputs
Dispatch Tasks
Identify Outputs
to Post
Post Outputs
A
B
C
D
E
F
G
H
I
ATR tasks
ANC tasks
