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Chapter 1
Getting Started with the cDAQ Chassis
cDAQ Module Interface
The cDAQ module interface manages data transfers between the STC3 and the C Series
modules. The interface also handles autodetection, signal routing, and synchronization.
STC3
The STC3 features independent high-speed data streams; flexible AI, AO, and DIO sample
timing, triggering, PFI signals for multi-device synchronization, flexible counter/timers with
hardware gating, digital waveform acquisition and generation, and static DIO.
•
AI, AO, and DIO Sample Timing
—The STC3 contains advanced AI, AO, and DIO
timing engines. A wide range of timing and synchronization signals are available through
the PFI lines. Refer to the following sections for more information about the configuration
of these signals:
–
The
Analog Input Timing Signals
section of Chapter 3,
Analog Input
–
The
Analog Output Timing Signals
section of Chapter 4,
Analog Output
–
The
Digital Input Timing Signals
section of Chapter 5,
Digital Input/Output and PFI
–
The
Digital Output Timing Signals
section of Chapter 5,
Digital Input/Output and PFI
•
Triggering Modes
—The cDAQ chassis supports different trigger modes, such as start
trigger, reference trigger, and pause trigger with analog, digital, or software sources. Refer
to the following sections for more information:
–
The
Analog Input Triggering Signals
section of Chapter 3,
Analog Input
–
The
Analog Output Triggering Signals
section of Chapter 4,
Analog Output
–
The
Digital Input Triggering Signals
section of Chapter 5,
Digital Input/Output and
PFI
–
The
Digital Output Triggering Signals
section of Chapter 5,
Digital Input/Output and
PFI
•
Independent Data Streams
—The cDAQ chassis supports seven independent high-speed
data streams, which allow for up to seven simultaneous hardware-timed tasks, such as
analog input, analog output, buffered counter/timers, and hardware-timed digital
input/output.
•
PFI Signals
—The PFI signals provide access to advanced features such as triggering,
synchronization, and counter/timers. You can also enable a programmable debouncing
filter on each PFI signal that, when enabled, samples the input on each rising edge of a filter
clock. PFI signals are available through parallel digital input and output modules installed
in up to two chassis slots and through the two PFI terminals provided on the cDAQ chassis.
Refer to the
PFI
section of Chapter 5,
Digital Input/Output and PFI
, for more information.
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