Index
©
National Instruments Corporation
I-17
DAQ-STC Technical Reference Manual
board environment setup, analog input
programming, 2-29 to 2-30
board power-up initialization
analog input programming, 2-27 to 2-28
primary analog output operation,
3-22 to 3-23
secondary analog output operation, 3-39
buffer timing and control for primary analog
output, 3-12 to 3-16
continuous mode, 3-13 to 3-14
master/slave trigger, 3-15 to 3-16
mute buffers, 3-15
single-buffer mode, 3-13
waveform staging, 3-14 to 3-15
buffered event counting
cumulative, 4-5
noncumulative, 4-4 to 4-5
programming, 4-20 to 4-22
Buffered_Period_And_Semi_Period_And_Pu
lse_Width_Measurement function,
4-26 to 4-27
buffered period measurement, 4-7 to 4-8
buffered pulse-train generation, 4-14
buffered pulsewidth measurement, 4-9
buffered retriggerable single pulse generation,
4-11 to 4-12
buffered semiperiod measurement, 4-8
buffered static pulse-train generation, 4-13
buffers, number of, primary analog output
operation, 3-24 to 3-26
bulletin board support, E-1
bus interface module, 9-1 to 9-8
features, 9-1
overview, 9-1
pin interface, 9-1 to 9-3
programming information, 9-3 to 9-5
bitfield descriptions, 9-4 to 9-5
write strobes, 9-4
timing diagrams, 9-5 to 9-8
Intel bus interface read timing
(figure), 9-6
Intel bus interface timing (table),
9-6 to 9-7
Intel bus interface write timing
(figure), 9-6
Motorola bus interface read timing
(figure), 9-7
Motorola bus interface timing
(table), 9-8
Motorola bus interface write timing
(figure), 9-8
C
channel selection, primary analog output
operation, 3-28
CHRDY_IN signal (table), 9-2
CHRDY_OUT signal
bus interface (table), 9-2
CPU-driven analog output, 3-6 to 3-7
CPU-driven analog output timing,
3-88 to 3-89
unbuffered data interface timing,
3-98 to 3-100
clock distribution, 10-2 to 10-3
master/slave distribution across RTSI bus
(figure), 10-2
programming, 10-10 to 10-11
timebases derived from IN_TIMEBASE
(table), 10-2 to 10-3
Clock_To_Board bit, 10-13
Clock_To_Board_Divide_By_2 bit, 10-13
configuration FIFO control, 2-7 to 2-9
configuration memory output, initializing,
2-28 to 2-29
configuration memory timing, 2-89 to 2-91
related signals (figure), 2-89
timing (table), 2-90
continuous acquisition mode, 2-15
continuous mode, buffer timing and control,
primary analog output, 3-13 to 3-14
Continuous_Pulse_Train_Generation
function, 4-30 to 4-31
