Index
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National Instruments Corporation
I-37
DAQ-STC Technical Reference Manual
STST_GATE signal
description (table), 2-119
external CONVERT mode, 2-10 to 2-11
synchronization, trigger selection and
conditioning
analog input timing/control
module, 2-122
analog output timing/control
module, 3-116
T
technical support, E-1 to E-2
telephone and fax support numbers, E-2
TEST_IN* signal (table), 10-10
test mode, 10-6 to 10-9
checking input pin connectivity, 10-7
input pin pairs (table), 10-8 to 10-9
internal gate tree structure (figure), 10-7
testing RESET pin, 10-8
TEST_OUT signal (table), 10-10
time measurement functions, 4-6 to 4-9
buffered period measurement, 4-7 to 4-8
buffered pulsewidth measurement, 4-9
buffered semiperiod measurement, 4-8
single-period measurement, 4-6 to 4-7
single-pulsewidth measurement, 4-7
timebases derived from IN_TIMEBASE
(table), 10-2 to 10-3
timing diagrams
analog input timing/control module,
2-84 to 2-111
basic analog input timing,
2-86 to 2-87
configuration memory, 2-89 to 2-91
CONVERT_SRC signal,
2-84 to 2-85
data FIFOs, 2-88
external CONVERT source,
2-92 to 2-93
external triggers, 2-93 to 2-97
maximum rate analog input,
2-91 to 2-92
OUT_CLK signal, 2-85
SCAN_IN_PROG deassertion, 2-103
signal definitions, 2-84 to 2-85
START trigger and
SCAN_IN_PROG assertion,
2-100 to 2-103
START1 and START2 triggers,
2-97 to 2-100
STOP trigger, 2-103 to 2-104
trigger output, 2-97 to 2-104
analog output timing/control module,
3-84 to 3-108
counter outputs, 3-107 to 3-108
CPU-driven analog output
timing, 3-88
DAQ-STC- and CPU-driven analog
output timing, 3-90 to 3-92
DAQ-STC-driven analog output
timing, 3-86 to 3-88
decoded signal timing, 3-94 to 3-95
external trigger timing,
3-102 to 3-104
local buffer mode timing,
3-96 to 3-97
maximum update rate timing,
3-101 to 3-102
secondary analog output timing, 3-93
signal definitions, 3-84 to 3-86
trigger output, 3-104 to 3-107
unbuffered data interface timing,
3-98 to 3-100
bus interface module, 9-5 to 9-8
Intel bus interface read timing
(figure), 9-6
Intel bus interface timing (table),
9-6 to 9-7
Intel bus interface write timing
(figure), 9-6
Motorola bus interface read timing
(figure), 9-7
