Index
DAQ-STC Technical Reference Manual
I-38
©
National Instruments Corporation
Motorola bus interface timing
(table), 9-8
Motorola bus interface write timing
(figure), 9-8
digital I/O, 7-15 to 7-16
serial input timing, 7-15 to 7-16
serial output timing, 7-16
general-purpose counter/timer,
4-53 to 4-56
CTR_U/D reference pin selection
(table), 4-54
CTRGATE reference pin selection
(table), 4-54
CTRSRC minimum period and
minimum pulsewidth
(figure), 4-55
CTRSRC reference pin selection
(table), 4-53
CTRSRC to CTROUT delay,
4-55 to 4-56
G_GATE minimum pulsewidth, 4-56
TMRDACREQ signal
DAQ-STC-driven analog output timing,
3-86 to 3-87
description (table), 3-19
serial link data interface, 3-10
simplified analog output model, 3-5
TMRDACWR* signal
DAC interface, 3-8
DAQ-STC- and CPU-driven analog
output timing, 3-91 to 3-92
DAQ-STC-driven analog output, 3-6
DAQ-STC-driven analog output timing,
3-86 to 3-88
description (table), 3-19
FIFO data interface, 3-9
local buffer mode, 3-9 to 3-10
local buffer mode timing, 3-96 to 3-97
maximum update rate timing, 3-101
serial link data interface, 3-10
simplified analog output model, 3-4
unbuffered data interface, 3-11
unbuffered data interface timing,
3-98 to 3-100
trigger, analog. See analog trigger circuit.
trigger output, analog input timing/control,
2-97 to 2-102
SCAN_IN_PROG deassertion, 2-103
START trigger and SCAN_IN_PROG
assertion, 2-100 to 2-102
external CONVERT mode, 2-102
internal CONVERT mode, 2-101
START1 and START2 triggers,
2-97 to 2-100
asynchronous mode, 2-99 to 2-100
synchronous mode, 2-97 to 2-99
STOP trigger, 2-103 to 2-104
asynchronous mode, 2-104
synchronous mode, 2-104
trigger output, analog output timing/control
module, 3-104 to 3-107
START1 trigger, asynchronous mode,
3-106 to 3-107
START1 trigger, synchronous mode,
3-104 to 3-106
trigger selection and conditioning
analog input timing/control module,
2-119 to 2-122
edge detection, 2-122
EXT_GATE routing logic
(figure), 2-121
PFI selectors (table), 2-121
START and STOP routing logic
(figure), 2-120
START1 and START2 routing logic
(figure), 2-120
synchronization, 2-122
trigger signals, 2-122 to 2-123
analog output timing/control module,
3-114 to 3-116
edge detection, 3-116
