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Chapter 6
Digital I/O
•
Case 2
—If an additional line on the bus also has a transition during the filter clock period,
the change is not propagated until the next filter clock edge, as shown in Figure 6-14.
Figure 6-14.
Case 2
Figure 6-15 illustrates the difference between line and bus filtering.
Figure 6-15.
Line and Bus Filtering
2A With line filtering, filtered input A would ignore the glitch on digital input P0.B and transition after two filter
clocks.
3A Filtered input A goes high when sampled high for two consecutive filter clocks and transitions on the next
filter edge because digital input P0.B glitches.
Digit
a
l Inp
u
t P0.A
Digit
a
l Inp
u
t P0.B
Filter Clock
Filtered Inp
u
t A
Filtered Inp
u
t B
Not
S
t
ab
le
Not
S
t
ab
le
Digit
a
l Inp
u
t P0.A
Digit
a
l Inp
u
t P0.B
Filter Clock
Filtered Inp
u
t A
Filtered Inp
u
t B
1A
2A
3
A
Summary of Contents for DAQ X NI 634 Series
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