© National Instruments
|
10-3
PXI Express Considerations
PXI clock and trigger signals are only available on PXI Express devices.
PXI and PXI Express Clock and Trigger Signals
Refer to the
,
,
,
, and
sections of Chapter 9,
, for more information about PXI and PXI Express clock and
trigger signals.
PXI Express
PXI Express X Series devices can be installed in any PXI Express slot in PXI Express chassis.
PXI Express specifications are developed by the PXI System Alliance (
www.pxisa.org
).
PXIe DAQ Bandwidth Considerations
In order to continuously transfer large amounts of data, the entire PXI Express system must be
designed with sufficient data bandwidth.
Depending on the PXI Express connection to the PXI Express chassis backplane, the bandwidth
bottleneck could be due to one of the following: the DAQ task, the backplane connection, a PCIe
switch integrated into the PXI Express backplane, or between the connection of a PXI Express
remote controller to a host machine (if using MXI).
Different PXI Express chassis have different architectures and per slot bandwidths.
If you are using a high channel count or high-speed MIO/SMIO DAQ device, pay special
attention to these factors since buffer overflow or underflow errors can occur as you approach
or pass the maximum theoretical system bandwidth.
Note
(NI PXIe-6386/6396 Devices)
PXIe-6386 and PXIe-6396 devices differ in
several ways from other SMIO devices. For more information about throughput
considerations for these devices, go to
ni.com/info
and enter the Info Code
smio14ms
.
USB DAQ Bandwidth Considerations
To transfer large amounts of data continuously, you must account for USB limitations. The
maximum theoretical bandwidth for USB 2.0 is 60 MB/s. Typical bandwidth to the host
computer from USB DAQ systems could produce lower speeds, depending on the application.
Tasks using multiple channels at higher sample rates may experience buffer overflow/underflow
errors.
Summary of Contents for DAQ X NI 634 Series
Page 1: ...PXIe 6349...
