Chapter 6
Digital I/O
X Series User Manual
6-8
ni.com
•
PXI_CLK10
•
RTSI <0..7>
•
PFI <0..15>
•
PXI_STAR
•
PXIe-DSTAR<A,B>
•
Analog Comparison Event (an analog trigger)
Refer to the Ro
u
ting Table in MAX for all additional ro
u
table signals.
DI Sample Clock Timebase is not available as an o
u
tp
u
t on the I/O
connector. DI Sample Clock Timebase is divided down to provide one of
the possible so
u
rces for DI Sample Clock. Yo
u
can config
u
re the polarity
selection for DI Sample Clock Timebase as either rising or falling edge
except for the 100 MHz Timebase or 20 MHz Timebase.
Yo
u
might
u
se DI Sample Clock Timebase if yo
u
want to
u
se an external
sample clock signal, b
u
t need to divide the signal down. If yo
u
want to
u
se
an external sample clock signal, b
u
t do not need to divide the signal, then
yo
u
sho
u
ld
u
se DI Sample Clock rather than DI Sample Clock Timebase.
DI Start Trigger Signal
Use the DI Start Trigger (di/StartTrigger) signal to begin a meas
u
rement
acq
u
isition. A meas
u
rement acq
u
isition consists of one or more samples.
If yo
u
do not
u
se triggers, begin a meas
u
rement with a software command.
Once the acq
u
isition begins, config
u
re the acq
u
isition to stop:
•
When a certain n
u
mber of points are sampled (in finite mode)
•
After a hardware reference trigger (in finite mode)
•
With a software command (in contin
u
o
u
s mode)
An acq
u
isition that
u
ses a start trigger (b
u
t not a reference trigger) is
sometimes referred to as a posttriggered acq
u
isition.
Retriggerable DI
The DI Start Trigger can also be config
u
red to be retriggerable. The timing
engine will generate the sample and convert clocks for the config
u
red
acq
u
isition in response to each p
u
lse on an DI Start Trigger signal.
The timing engine ignores the DI Start Trigger signal while the clock
generation is in progress. After the clock generation is finished, the timing
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