Chapter 4
Analog Input
X Series User Manual
4-34
ni.com
Figure 4-20.
AI Sample Clock and AI Convert Clock Improperly Matched;
Leads to Aperiodic Sampling
Figure 4-21.
AI Sample Clock and AI Convert Clock Properly Matched
AI Convert Clock Timebase Signal
The AI Convert Clock Timebase (ai/ConvertClockTimebase) signal is
divided down to provide one of the possible so
u
rces for AI Convert Clock.
Use one of the following signals as the so
u
rce of AI Convert Clock Timebase:
•
AI Sample Clock Timebase
•
100 MHz Timebase
AI Convert Clock Timebase is not available as an o
u
tp
u
t on the I/O
connector.
AI Hold Complete Event Signal
The AI Hold Complete Event (ai/HoldCompleteEvent) signal generates
a p
u
lse after each A/D conversion begins. Yo
u
can ro
u
te AI Hold Complete
Event o
u
t to any PFI <0..15>, RTSI <0..7>, or PXIe-DSTARC terminal.
The polarity of AI Hold Complete Event is software-selectable, b
u
t is
typically config
u
red so that a low-to-high leading edge can clock external
AI m
u
ltiplexers indicating when the inp
u
t signal has been sampled and can
be removed.
AI
Sa
mple Clock
AI Convert Clock
Sa
mple #1
Sa
mple #2
Sa
mple #
3
1 2
3
0
0
Ch
a
nnel Me
asu
red
1 2
3
0
AI
Sa
mple Clock
AI Convert Clock
Sa
mple #1
Sa
mple #2
Sa
mple #
3
Ch
a
nnel Me
asu
red
1 2
3
0
1 2
3
0 1
2
3
0
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