B-4
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Appendix B
Timing Diagrams
Figure B-2.
Input Timing and the Analog Input Timing Engine
Figure B-3.
Input Timing Diagram
Table B-1.
Input Timing
Time
From
To
Min (ns)
Max (ns)
t
1
*
PFI
PFI_i
4.2
6.4
15.2
19.2
RTSI
RTSI_i
0.9
2.2
2.0
3.0
STAR
STAR_i
0.9
—
—
2.8
*
The delay ranges given for PFI and RTSI represent the fastest and slowest terminal routing within the
trigger group for a given condition (maximum or minimum timing). This difference can be useful when
two external signals will be used together and the relative timing between the signals is important.
Start Trigger
Terminal
Selected Reference Trigger
Reference Trigger
Terminal
Terminal
Selected Sample Clock
Terminal
Terminal
Terminal
Selected Start Trigger
RTSI
Terminal
Terminal
Terminal
Selected Pause Trigger
SI
Counter
Block
SI2
Counter
Block
SI_TC
Sample Clock Timebase
Sync Sample Clock Timebase
Convert Clock Timebase
Sync Convert Clock Timebase
SI Start
Pause Trigger
p_AI_Convert
Start
1
SI2_TC
_i
_i
_i
_i
_i
Terminal
_i
t
1
t
1
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