B-8
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Appendix B
Timing Diagrams
Figure B-6.
Convert Clock and the Analog Input Timing Engine
Figure B-7.
Convert Clock Timing Diagram
Table B-3.
Convert Clock Timing
Time
Description
Line
Min (ns)
Max (ns)
t
8
Delay from _i to Sync Convert Clock
Timebase
PFI
6.4
15.9
RTSI
6.0
15.6
STAR
5.7
12.9
Start Trigger
Terminal
Selected Reference Trigger
Reference Trigger
Terminal
Terminal
Selected Sample Clock
Terminal
Terminal
Terminal
Selected Start Trigger
RTSI
Terminal
Terminal
Terminal
Selected Pause Trigger
SI
Counter
Block
SI2
Counter
Block
SI_TC
Sample Clock Timebase
Sync Sample Clock Timebase
Convert Clock Timebase
Sync Convert Clock Timebase
SI Start
p_AI_Convert
Start
1
SI2_TC
Pause Trigger
_i
POUT
Sync Convert Clock Timebase
Convert Clock Timebase
p_AI_Convert
t
8
t
9
t
10
t
11
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