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5-9
M Series User Manual
Routing AO Sample Clock Signal to an Output Terminal
You can route AO Sample Clock (as an active low signal) out to any PFI <0..15> or RTSI <0..7>
terminal.
Other Timing Requirements
A counter on your device internally generates AO Sample Clock unless you select some external
source. AO Start Trigger starts the counter and either the software or hardware can stop it once
a finite generation completes. When using an internally generated AO Sample Clock, you also
can specify a configurable delay from AO Start Trigger to the first AO Sample Clock pulse. By
default, this delay is two ticks of AO Sample Clock Timebase.
Figure 5-6 shows the relationship of AO Sample Clock to AO Start Trigger.
Figure 5-6.
AO Sample Clock and AO Start Trigger
AO Sample Clock Timebase Signal
The AO Sample Clock Timebase (ao/SampleClockTimebase) signal is divided down to provide
a source for AO Sample Clock.
You can route any of the following signals to be the AO Sample Clock Timebase signal:
•
20 MHz Timebase
•
100 kHz Timebase
•
PXI_CLK10
•
PFI <0..15>
•
RTSI <0..7>
•
PXI_STAR
•
Analog Comparison Event (an analog trigger)
AO Sample Clock Timebase is not available as an output on the I/O connector.
AO Sample Clock Timebase
AO Start Trigger
AO Sample Clock
Delay
From
Start
Trigger
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