NI 5731/5732/5733/5734R User Guide and Specifications
12
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Creating a LabVIEW Project and Running a VI on an FPGA Target
This section explains how to set up your target and create an FPGA VI and host VI for data
communication. For more detailed information about acquiring data on your NI 5731/5732/5733/5734,
refer to the device specific examples available in NI Example Finder.
Creating a Project
1.
Launch LabVIEW, or if LabVIEW is already running, select
File»New
.
2.
In the
New
dialog box, select
Project»Empty Project
and click
OK
. The new project opens in the
Project Explorer
window.
3.
Save the project as
573xSampleAcq.lvproj
.
Creating an FPGA Target VI
1.
In the
Project Explorer
window, right-click
My Computer
and select
New»Targets and
Devices
.
2.
In the
Add Targets and Devices on My Computer
dialog box, select the
Existing Target or
Device
button and expand
FPGA Target
. The target is displayed.
3.
Select your device and click
OK
. The target and target properties are loaded into the
Project
Explorer
window.
4.
In the
Project Explorer
window, expand
FPGA Target (RIO
x
, PXI-79
xx
R)
.
5.
Right-click
FPGA Target (RIO
x
, PXI-79
xx
R)
and select
New»FPGA Base Clock
.
6.
In the
Resource
pull-down menu, select
IO Module Clock 0
.
7.
Enter the default Sample clock rate for your device (
40
,
80
, or
120
) in the
Compile for single
frequency
control and click
OK
.
8.
Right-click
IO Module
in the
Project Explorer
window and select
Properties
.
9.
Select the NI 573
x
from the IO Module list. The available CLIP for the NI 5731/5732/5733/5734
is displayed in the
General
category of the Component Level IP pane. If the information in the
General
category is dimmed, select the
Enable IO Module
checkbox.
10. Select
NI 573x CLIP
in the
Name
list box of the Component Level IP section.
11. In the
Clock Selections
category, leave
Clk40
configured as the
Top-Level Clock
. This step is
necessary to compile the FPGA VI correctly.
12. Click
OK
.
Note
Configuring this clock is required for proper CLIP operation. Refer to the
NI 5731/5732/5733/5734 CLIP topics in the
NI FlexRIO Help
for more information about
configuring your clocks.
13. In the
Project Explorer
window, right-click the FPGA target and select
New»VI
. A blank VI
opens.
14. Select
Window»Show Block Diagram
to open the VI block diagram.
15. In the
Project Explorer
window, expand the
IO Module (NI 573x: NI 573x)
tree view.
16. Drag
AI 0
to the block diagram.
17. Add a Timed Loop structure around the single node.
18. Wire an indicator to the output terminal of the
IO Module\AI 0 Data N
node.
19. Wire an
FPGA Clock Constant
to the input node of the Timed Loop. Set this constant to
IO Module Clock 0
.
Summary of Contents for NI 5734
Page 1: ...NI 5734...
