Chapter 7
Counters
©
National Instruments Corporation
7-23
Figure 7-25 shows a block diagram of the frequency generator.
Figure 7-25.
Frequency Generator Block Diagram
The frequency generator generates the Frequency Output signal. The
Frequency Output signal is the Frequency Output Timebase divided by a
number you select from 1 to 16. The Frequency Output Timebase can be
either the 20 MHz Timebase divided by 2 or the 100 kHz Timebase.
The duty cycle of Frequency Output is 50% if the divider is either 1 or
an even number. For an odd divider, suppose the divider is set to D.
In this case, Frequency Output is low for (D + 1)/2 cycles and high for
(D – 1)/2 cycles of the Frequency Output Timebase.
Figure 7-26 shows the output waveform of the frequency generator when
the divider is set to 5.
Figure 7-26.
Frequency Generator Output Waveform
Frequency Output can be routed out to any PFI <0..15> or RTSI <0..7>
terminal. All PFI terminals are set to high-impedance at startup. The FREQ
OUT signal also can be routed to DO Sample Clock and DI Sample Clock.
In software, program the frequency generator as you would program one of
the counters for pulse train generation.
For information about connecting counter signals, refer to the
section.
100 kHz Time
bas
e
20 MHz Time
bas
e
Fre
qu
ency
O
u
tp
u
t
Time
bas
e
FREQ OUT
Divi
s
or
(1–16)
Fre
qu
ency Gener
a
tor
÷
2
Frequency
Output
Timebase
FREQ OUT
(Divisor = 5)
