Chapter 9
Digital Routing and Clock Generation
9-10
ni.com
The filter setting for each input can be configured independently. On power
up, the filters are disabled. Figure 9-4 shows an example of a low to high
transition on an input that has its filter set to 125 ns (N = 5).
Figure 9-4.
Filter Example
Enabling filters introduces jitter on the input signal. For the 125 ns and
6.425 µs filter settings, the jitter is up to 25 ns. On the 2.56 ms setting,
the jitter is up to 10.025 µs.
When a PFI input is routed directly to RTSI, or a RTSI input is routed
directly to PFI, the M Series device does not use the filtered version of the
input signal.
Refer to the KnowledgeBase document,
Digital Filtering with M Series
,
for more information about digital filters and counters. To access this
KnowledgeBase, go to
ni.com/info
and enter the info code
rddfms
.
Table 9-3.
Filters
Filter Setting
N (Filter Clocks
Needed to
Pass Signal)
Pulse Width
Guaranteed to
Pass Filter
Pulse Width
Guaranteed to
Not Pass Filter
125 ns
5
125 ns
100 ns
6.425 µs
257
6.425 µs
6.400 µs
2.56 ms
~101,800
2.56 ms
2.54 ms
Disabled
—
—
—
1 2
3
1 4
1
2
3
4 5
RT
S
I, PFI, or
PXI_
S
TAR Termin
a
l
Filter Clock
(40 MHz)
Filtered Inp
u
t
Filtered inp
u
t goe
s
high when termin
a
l
i
s
sa
mpled high on
five con
s
ec
u
tive filter
clock
s
.
