Chapter 10
Bus Interface
10-2
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transferred simultaneously between the ports. The DMA controller
supports burst transfers to and from the FIFO.
Each DMA controller supports several features to optimize PCI/PXI bus
utilization. The DMA controllers pack and unpack data through the FIFOs.
This feature allows the DMA controllers to combine multiple 16-bit
transfers to the DAQ circuitry into a single 32-bit burst transfer on PCI. The
DMA controllers also automatically handle unaligned memory buffers on
PCI/PXI.
Each DMA controller supports packing and unpacking of data through the
FIFOs to connect different size devices and optimize PCI bus utilization
and automatically handles unaligned memory buffers.
M Series USB devices have four fully-independent USB Signal Stream for
high-performance transfers of data blocks. These channels are assigned to
the first four measurement/acquisition circuits that request one.
PXI Considerations
Note
PXI clock and trigger signals are only available on PXI devices.
PXI Clock and Trigger Signals
Refer to the
,
,
, and
sections of Chapter 9,
, for more information about PXI clock and trigger signals.
PXI and PXI Express
NI PXI M Series devices can be installed in any PXI chassis and most slots
of PXI Express hybrid chassis. NI PXI Express M Series devices can be
installed in any PXI Express slot in PXI Express chassis.
PXI specifications are developed by the PXI System Alliance
(
www.pxisa.org
). Using the terminology of the PXI specifications, some
NI PXI M Series devices are
3U Hybrid Slot-Compatible PXI-1 Peripheral
Modules
. Refer to your device specifications to see if your PXI M Series
device is hybrid slot-compatible.
3U
designates devices that are 100 mm tall (as opposed to the taller
6U modules).
