Chapter 2
Device Overview
2-4
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Figure 2-3.
Counters 0 and 1 at Gate Edge on PFI 38 at the Same Time
Duplicate Count Prevention
D
u
plicate co
u
nt prevention (or synchrono
u
s co
u
nting mode) ens
u
res that a
co
u
nter ret
u
rns correct data in applications that are a slow or non-periodic
external so
u
rce. D
u
plicate co
u
nt prevention applies only to b
u
ffered
co
u
nter applications s
u
ch as meas
u
ring freq
u
ency or period.
For s
u
ch b
u
ffered applications, the co
u
nter sho
u
ld store the n
u
mber of
times an external so
u
rce p
u
lses between rising edges on the Gate signal.
Counter
Source
PFI 38
at CTR 0 GATE
PFI 38
at CTR 1 GATE
Sampled
GATE at Ctr0
Sampled
GATE at Ctr1
1/2 Cycles
1/4 Cycle
PFI 38
at Input To ASIC
PFI 38
Synchronized at Pad
