Appendix A
Specifications
©
National Instruments
A-7
NI PXIe-1071 User Manual
System Synchronization Clocks
(PXI_CLK10, PXIe_CLK100, PXIe_SYNC100)
10 MHz System Reference Clock: PXI_CLK10
Maximum slot-to-slot skew ................... 500 ps
Accuracy ................................................ ±25 ppm max (guaranteed over
the operating temperature range)
Maximum jitter ...................................... 5 ps RMS phase-jitter
(10 Hz-1 MHz range)
Duty-factor ............................................. 45%-55%
Unloaded signal swing ........................... 3.3 V ±0.3 V
Note
For other specifications refer to the
PXI-1 Hardware Specification
.
100 MHz System Reference Clock: PXIe_CLK100 and
PXIe-SYNC100
Maximum slot-to-slot skew ................... 100 ps
Accuracy ................................................ ±25 ppm max (guaranteed over
the operating temperature range)
Maximum jitter ...................................... 3 ps RMS phase-jitter
(10 Hz-12 kHz range)
2 ps RMS phase-jitter
(12 kHz-20 MHz range)
Duty-factor for PXIe_CLK100 .............. 45%-55%
Absolute differential voltage
(When terminated with a 50
Ω
load
to 1.30 V or Thévenin equivalent) ......... 400-1000 mV
Note
For other specifications refer to the
PXI-5 PXI Express Hardware Specification
.
DMA Support
For more information about this chassis’ support of hardware modules
with 64-bit DMA and/or 32-bit DMA with PAE mode, please visit
ni.com/info
and enter the Info Code
PXI64HANG
.
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