© National Instruments
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B-25
Figure B-30 shows the external trigger and external clock and the trigger delay and clock delay.
Figure B-30.
External Trigger and External Clock Application
To satisfy the DFF setup and hold requirement, the following condition must be true:
External
Setup
≥
DFF
Setup
- Cloc TriggerDelay
External
Hold
≥
DFF
Hold
+ ClockDelay - TriggerDelay
DFF
Setup
and DFF
Hold
are given by Table B-16 for AO Start Trigger and Table B-18 for AO
Pause triggers.
ClockDelay is the sum of the input timing, shown in Table B-12, and insertion timing, shown in
Table B-13.
TriggerDelay is the sum of the input timing, shown in Table B-12, and internal timing, shown in
Tables B-15 and B-17.
For setup calculations, use the maximum timing parameters. For hold calculations, use the
minimum timing parameters.
For input timing, as shown in Table B-12, two numbers are given for the maximum delay and
two numbers for the minimum delay. In order to account for the worst case skew between
different input terminals, use the range given in the input delay tables in the
in a way that provides the most conservative results. For setup calculations, use the bigger
number for TriggerDelay and the smaller number ClockDelay. For hold calculations, use the
smaller number for TriggerDelay and the larger number for ClockDelay.
Output Timing
The analog output timer has three possible trigger outputs—Start Trigger, Pause Trigger, and
Sample Clock. The delays presented in this section assume a 200 pF load on PFI lines and a
50 pF load on RTSI lines. Actual delays will vary with the actual load. The two numbers given
for each condition represent the variation from the best case and worst case terminals.
•
Start Trigger
—As an output, the Start Trigger is routed as an asynchronous pulse. The
actual signal that gets routed is the Selected Start Trigger signal, so there is no synchronous
delay involved.
DFF
D
Q
Extern
a
l
Trigger
Extern
a
l
Clock
TriggerDel
a
y
ClockDel
a
y
Summary of Contents for PCI-6281
Page 1: ...PCI 6281...
