© National Instruments
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B-39
Figure B-50 and Table B-34 show the output delays.
Figure B-50.
Output Delays
Gating Modes
Gating mode refers to how the counter/timer uses the Gate input. Some timing operations depend
on the gating mode. Depending on the application, the counter/timers either level gating mode
or edge gating mode.
In NI-DAQmx, the counter/timers use level gating mode for the following measurements:
•
Edge counting
•
Pulse width measurements
•
Two-signal edge separation measurements
All other measurements use edge gating mode.
Table B-34.
Output Delays Timing
Time
Line
Min (ns)
Max (ns)
t
10
—
1.0
4.0
t
11
PFI
7.5
28.2
RTSI
6.5
18.0
t
12
PFI
8.5
32.2
RTSI
7.5
22.0
t
13
PFI
7.5
28.7
RTSI
6.5
18.0
t
10
t
11
t
12
t
1
3
S
elected
S
o
u
rce
PFI, RT
S
I
(Co
u
nter
n
G
a
te)
S
elected G
a
te
PFI, RT
S
I
(Co
u
nter
n
S
o
u
rce)
PFI, RT
S
I
(Co
u
nter
n
Intern
a
l O
u
t)
O
u
t_o
Summary of Contents for PCI-6281
Page 1: ...PCI 6281...
