B-42
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Appendix B
Timing Diagrams
Table B-37 shows delays for generating different clocks using an External Reference Clock and
the PLL.
Figure B-53.
Generating Different Clocks Using an External Reference Clock and the PLL
Table B-37.
Generating Different Clocks Using an External Reference Clock and the PLL
Time
From
To
Min (ns)
Max (ns)
t
4
80 MHz Timebase
20 MHz Timebase
1.5
5.0
t
5
The source of the external
reference clock
(RTSI <0..7>, STAR_TRIG, PX
I_CLK10)
80 MHz Timebase
(through PLL_OUT)
1.0
5.5
RT
S
I <0..7>
S
TAR_TRIG
PXI_CLK10
(Reference Clock)
8
0 MHz Time
bas
e (PLL)
20 MHz Time
bas
e (PLL)
t
4
t
5
Summary of Contents for PCI-6281
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