©
National Instruments Corporation
19
18-Slot NI PXIe-1065 Backplane Installation Guide
External 10 MHz Reference Out (on J206)
Accuracy ................................................ ±25 ppm max. (guaranteed over
the operating temperature range)
Maximum jitter ...................................... 5 ps RMS phase-jitter
(10 Hz–1 MHz range)
Output amplitude.................................... 1 V
PP
±20% square-wave
into 50
Ω
2 V
PP
unloaded
Output impedance .................................. 50
Ω
±5
Ω
External Clock Source
Frequency............................................... 10 MHz ±100 PPM
Input amplitude
J206 ................................................. 200 mV
PP
to 5 V
PP
square-wave
or sine-wave
System timing slot
PXI_CLK10_IN.............................. 5 V or 3.3 V TTL signal
J206 input impedance............................. 50
Ω
±5
Ω
Maximum jitter introduced
by backplane .......................................... 1 ps RMS phase-jitter
(10 Hz–1 MHz range)
PXIe_SYNC_CTRL
V
IH
.......................................................... 2.0–5.5 V
V
IL
.......................................................... 0–0.8 V
PXI Star Trigger
Maximum slot-to-slot skew ................... 250 ps
Backplane characteristic impedance ...... 65
Ω
±10%
Notes
For PXI slot to PXI Star mapping, refer to the
System Timing Slot
section of
Chapter 1,
Getting Started
, in the
NI PXIe-1065 User Manual
.
For other specifications, refer to the
PXI-1 Hardware Specification
.
