18-Slot NI PXIe-1065 Backplane Installation Guide
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Note
Although you can route any trigger line in either direction, you cannot route it in
more than one direction at a time.
System Reference Clock
The NI PXIe-1065 backplane supplies the PXI 10 MHz system clock signal
(PXI_CLK10) independently driven to each peripheral slot, and
PXIe_CLK100 and PXIe_SYNC100 to the PXI Express slots, hybrid slots,
and system timing slot.
An independent buffer (having a source impedance matched to the
backplane and a skew of less than 1 ns between slots) drives PXI_CLK10
to each peripheral slot. Refer to Figure 4 for the PXI_CLK10 routing
configuration. You can use this common reference clock signal to
synchronize multiple modules in a measurement or control system.
An independent buffer drives PXIe_CLK100 to the PXI Express peripheral
slots, hybrid peripheral slots, and system timing slot. Refer to Figure 4 for
the routing configuration of PXIe_CLK100. These clocks are matched in
skew to less than 100 ps. The differential pair must be terminated on the
peripheral with LVPECL termination for the buffer to drive PXIe_CLK100,
so that when there is no peripheral or a peripheral that does not connect to
PXIe_CLK100, no clock is driven on the pair to that slot.
An independent buffer drives PXIe_SYNC100 to the PXI Express
peripheral slots, hybrid peripheral slots, and system timing slot. Refer to
Figure 4 for the routing configuration of PXIe_SYNC100. The differential
pair must be terminated on the peripheral with LVPECL termination for the
buffer to drive PXIe_SYNC100, so that when there is no peripheral or a
peripheral that does not connect to PXIe_SYNC100, no SYNC100 signal
is driven on the pair to that slot.
