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Chapter 1
Getting Started
An independent buffer drives PXIe_SYNC100 to the PXI Express peripheral slots, hybrid
peripheral slots, and system timing slot. Refer to Figure 1-5 for the routing configuration of
PXIe_SYNC100. The differential pair must be terminated on the peripheral with LVPECL
termination for the buffer to drive PXIe_SYNC100 so that when there is no peripheral or a
peripheral that does not connect to PXIe_SYNC100, there is no SYNC100 signal being driven
on the pair to that slot.
Figure 1-5.
Distribution of PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100
PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 have the default timing relationship
described in Figure 1-6.
Figure 1-6.
System Reference Clock Default Behavior
P2
P1
XP4
XP
3
TP2
T
P1
P2
P1
P2
P1
P2
P1
P1
P1
P1
XP4
XP
3
XP4
XP
3
XP4
XP
3
XP4
XP
3
XP4
XP
3
XP4
XP
3
XP4
XP
3
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
XP4
XP
3
XP2
XP1
P1
10 MHz
REF IN
10 MHz
REF OUT
PXI_CLK10_IN
1
8
9
10
PXIe_CLK100
PXIe_
S
YNC100
PXI_CLK10
7
H
11
H
H
12
H
1
3
14
15
6
5
4
3
2
16
17
1
8
PXIe_CLK100
PXI_CLK10
PXIe_
S
YNC100
0 1 2
3
4 5 6 7
8
9 0 1 2
3
4 5 6 7
8
9 0 1 2
3
4 5 6 7
8
9