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1-9
PXI Trigger Bus
All slots on the same PXI bus segment share eight PXI trigger lines. You can use these trigger
lines in a variety of ways. For example, you can use triggers to synchronize the operation of
several different PXI peripheral modules. In other applications, one module located in the
system timing slot can control carefully timed sequences of operations performed on other
modules in the system. Modules can pass triggers to one another, allowing precisely timed
responses to asynchronous external events the system is monitoring or controlling.
The PXI trigger lines from adjacent PXI trigger bus segments can be routed in either direction
across the PXI trigger bridges through buffers. This allows you to send trigger signals to, and
receive trigger signals from, every slot in the chassis. Static trigger routing (user-specified line
and directional assignments) can be configured through Measurement & Automation Explorer
(MAX). Dynamic routing of triggers (automatic line assignments) is supported through certain
National Instruments drivers like NI-DAQmx.
Note
Although any trigger line may be routed in either direction, it cannot be
routed in more than one direction at a time.
System Reference Clock
The PXIe-1066DC chassis supplies the PXI 10 MHz system clock signal (PXI_CLK10)
independently driven to each peripheral slot and PXIe_CLK100 and PXIe_SYNC100 to the
PXI Express slots, hybrid slots, and system timing slot.
An independent buffer (having a source impedance matched to the backplane and a skew of less
than 1 ns between slots) drives PXI_CLK10 to each peripheral slot. Refer to Figure 1-5 for the
routing configuration of PXI_CLK10. You can use this common reference clock signal to
synchronize multiple modules in a measurement or control system.
An independent buffer drives PXIe_CLK100 to the PXI Express peripheral slots, hybrid
peripheral slots, and system timing slot. Refer to Figure 1-5 for the routing configuration of
PXIe_CLK100. These clocks are matched in skew to less than 100 ps. The differential pair must
be terminated on the peripheral with LVPECL termination for the buffer to drive PXIe_CLK100
so that when there is no peripheral or a peripheral that does not connect to PXIe_CLK100, there
is no clock being driven on the pair to that slot.
