© National Instruments
|
1-11
To synchronize the system to an external clock, you can drive PXI_CLK10 from an external
source through the PXI_CLK10_IN pin on the System Timing Slot. Refer to Table B-8,
Connector Pinout for the System Timing Slot
, for the pinout. When a 10 MHz clock is detected
on this pin, the backplane automatically phase-locks the PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 signals to this external clock and distributes these signals to the slots (refer to
Figure 1-5 for the distribution of PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100). Refer to
Appendix A,
, for the specification information for an external clock provided on
the PXI_CLK10_IN pin of the system timing slot.
You also can drive a 10 MHz clock on the 10 MHz REF IN connector on the front of the chassis.
When a 10 MHz clock is detected on this connector, the backplane automatically phase-locks
the PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100 signals to this external clock and
distributes these signals to the slots (refer to Figure 1-5 for the distribution of PXI_CLK10,
PXIe_CLK100 and PXIe_SYNC100). Refer to Appendix A,
, for the specification
information for an external clock provided on the 10 MHz REF IN connector on the rear panel
of the chassis.
If the 10 MHz clock is present on both the PXI_CLK10_IN pin of the System Timing Slot and
the 10 MHz REF IN connector on the front of the chassis, the signal on the System Timing Slot
is selected. Refer to Table 1-1 which explains how the 10 MHz clocks are selected by the
backplane.
A copy of the backplane’s PXI_CLK10 is exported to the 10 MHz REF OUT connector on the
front of the chassis. This clock is driven by an independent buffer. Refer to Appendix A,
, for the specification information for the 10 MHz REF OUT signal on the front
panel of the chassis.
Table 1-1.
Backplane External Clock Input Truth Table
System Timing Slot
PXI_CLK10_IN
Front Chassis Panel
10 MHz REF IN
Backplane PXI_CLK10,
PXIe_CLK100 and PXIe_SYNC100
No clock present
No clock present
Backplane generates its own clocks
No clock present
10 MHz clock present
PXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 all phase-locked to
Rear Chassis Panel—10 MHz REF IN
10 MHz clock present
No clock present
PXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 all phase-locked to
System Timing Slot—PXI_CLK10_IN
10 MHz clock present
10 MHz clock present
PXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 all phase-locked to
System Timing Slot—PXI_CLK10_IN
