System Timing Slot
The system timing slot is slot 10. The system timing slot accepts the following peripheral
modules:
•
A PXI Express System Timing Module with x8, x4, or x1 PCI Express link to the system
slot through a PCI Express switch. Each PXI Express peripheral slot can link up to a
Gen-2 x8 PCI Express, providing a maximum nominal single-direction bandwidth of 4
GB/s.
•
A PXI Express Peripheral with x8, x4, or x1 PCI Express link to the system slot through a
PCI Express switch.
•
A CompactPCI Express Type-2 Peripheral with x8, x4, or x1 PCI Express link to the
system slot through a PCI Express switch.
The system timing slot has three (3) dedicated differential pairs (PXIe_DSTAR) connected
from the TP1 and TP2 connectors to the XP3 connector for each PXI Express hybrid
peripheral slot, as well as routed back to the XP3 connector of the system timing slot, as
shown in the following figure. You can use the PXIe_DSTAR pairs for high-speed triggering,
synchronization, and clocking. Refer to the
PXI Express Specification
for details.
The system timing slot also has a single-ended (PXI Star) trigger connected to every slot.
Refer to the following figure for more details.
The system timing slot has a pin (PXI_CLK10_IN) through which a system timing module
may source a 10 MHz clock to which the backplane phase-locks. Refer to the System
Reference Clock section for details.
The system timing slot has a pin (PXIe_SYNC_CTRL) through which a system timing module
can control the PXIe_SYNC100 timing. Refer to the PXI Express Specification and the PXIe
SYNC CTRL section of this chapter for details.
Figure 4. PXIe_DSTAR and PXI Star Connectivity Diagram
1
2
H
3
H
4
H
5
H
6
H
7
H
8
H
9
H
10
11
H
12
H
13
H
14
H
15
H
16
H
17
H
18
H
DSTAR 6
DSTAR 5
DSTAR 7
DSTAR 4
DSTAR 3
DSTAR 2
DSTAR 1
DSTAR 15
DSTAR 14
DSTAR 13
DSTAR 16
DSTAR 12
DSTAR 11
DSTAR 10
STAR 7
STAR 8
STAR 6
STAR 5
STAR 4
STAR 3
STAR 2
STAR
1
STAR 10
STAR 11
STAR 12
STAR 13
STAR 14
STAR 15
STAR 16
DST
AR 8
DST
AR 9
DST
AR 0
ST
AR 9
ST
AR 0
8
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PXIe-1086DC User Manual and Specifications
