Figure 4. Carrier Block Diagram (KU035)
DIO Connector
(Front Panel)
Adapter Module
Connector
+5 V
+1.8 V
+12 V
GPIO
Configuration, GPIO
MGTs
Reference Clock
Power Supplies
Flash
FPGA
PXIe Connectors
PXI Triggers
Clk 100
DStarB, DStarC
Gen3 x8 PCIe
+12 V, +3.3 V
+12 V
Clk 10
Module Clocking
Synchronization
The following figure shows a block diagram of the carrier portion of the PXIe-5785 (KU040
and KU060 FPGA options).
Figure 5. Carrier Block Diagram (KU040 and KU060)
DIO Connector
(Front Panel)
Adapter Module
Connector
+5 V
+1.8 V
+12 V
GPIO
Configuration, GPIO
MGTs
Reference Clock
Power Supplies
Flash
FPGA
PXIe Connectors
PXI Triggers
Clk 100
DStarB, DStarC
Gen3 x8 PCIe
+12 V, +3.3 V
+12 V
Clk 10
Module Clocking
Synchronization
MGTs
DRAM Bank 0
(2 GB)
DRAM Bank 1
(2 GB)
The following figure shows a block diagram of the I/O portion of the PXIe-5785.
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PXIe-5785 Getting Started Guide
