Figure 6. PXIe-5785 Block Diagram
EXTERNAL REF/SCLK
CLK IN SMA
DAC38RF82
Dual 12-bit, 6.4 GS/s
AI1 SMA
ADC12DJ3200
Dual 12-bit, 3.2 GS/s
Single 12-bit, 6.4 GS/s
AI0 SMA
ANALOG INPUT
ANALOG OUTPUT
AC (Balun)
Coupled Path
AC (Balun)
Coupled Path
AO0 SMA
AC (Balun)
Coupled Path
Optional
Anti-Image Filter
Adapter Module
Connector
CLOCKING
AO1 SMA
AC (Balun)
Coupled Path
Optional
Anti-Image Filter
Component-Level Intellectual Property (CLIP)
The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for HDL
IP integration. FlexRIO devices support two types of CLIP: user-defined and socketed.
•
User-defined CLIP
allows you to insert HDL IP into an FPGA target, enabling VHDL
code to communicate directly with an FPGA VI.
•
Socketed CLIP
provides the same IP integration of the user-defined CLIP, but it also
allows the CLIP to communicate directly with circuitry external to the FPGA. Adapter
module socketed CLIP allows your IP to communicate directly with both the FPGA VI
and the external adapter module connector interface.
The PXIe-5785 ships with socketed CLIP items that add module I/O to the LabVIEW project.
PXIe-5785 Getting Started Guide
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© National Instruments
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