Glossary
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National Instruments Corporation
G-3
bus error
an error that signals failed access to an address. Bus errors occur with
low-level accesses to memory and usually involve hardware with bus
mapping capabilities. For example, nonexistent memory, a nonexistent
register, or an incorrect device access can cause a bus error.
C
C
Celsius
CLK10
a 10 MHz, ±100 ppm, individually buffered (to each module slot),
differential ECL system clock that is sourced from Slot 0 of a VXIbus
mainframe and distributed to Slots 1 through 12 on P2. It is distributed to
each slot as a single-source, single-destination signal with a matched delay
of under 8 ns.
CMOS
Complementary Metal Oxide Semiconductor; a process used in making
chips
D
DIN
Deutsches Institut für Normung—German Standards Institute
DMA
Direct Memory Access; a method by which data is transferred between
devices and internal memory without intervention of the central processing
unit. DMA is the fastest method of transferring data to/from computer
memory.
DRAM
Dynamic RAM (Random Access Memory); storage that the computer must
refresh at frequent intervals
E
ECL
Emitter-Coupled Logic
EDO
Extended Data Out; a DRAM architecture that shortens overall access
latency, improving performance
EEPROM
Electronically Erasable Programmable Read Only Memory—ROM that
can be erased with an electrical signal and reprogrammed
