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To look at the data that you have just captured, left click
on the “Plot_Data” button. If you have collected data with
a 12-bit ADC at 52MSPS and a -2dBFS sinewave input at
5MHz, you will see two’s complement data that looks like this: 

Next, left click on the 12B_FFT button, and you will see
the following FFT plot and performance summary. (Note
that if you are testing a 14-bit ADC you should set SW1
accordingly and click on the 14B_FFT button instead.) 

For more information on the Matlab routines, please refer
to section IV of this manual or the “analysis.txt” file in the
Mfiles directory. 

 

Configuring for Histogram Capture
(DNL and INL Analysis)

 

To configure the board for histogram capture, right click
on the capture control panel, then left click on “Configure
Capture.” You will see the capture configuration menu: 

Select 

 

“Histogram Debug”

 

, as shown above, and click on

 

“OK”.

 

 When the data capture control panel returns, you

can verify your capture settings by positioning the mouse
over the progress bar. You will see the following display:

 

When you press Start now, the SRAM will be cleared and
then the board will count the number of times each code
is output. When any count reaches the number that you
set with DIP switches 4 and 5, the counting will stop and
the data will be transferred. At 52 MSPS and a maximum
count of 16384, the counting takes about 1 second. You
will see LED1 flash as data is written to and read from the
SRAM. LED2 will again light for about 10-15 seconds as
the data is transferred to the PC and stored in the file that
you have selected. To use the included m-files to analyze
the histogram data and extract the DNL and INL of the
ADC, start Matlab and run 

 

“analysis_menu”

 

. If you still

have the Matlab analysis menu visible you can again click
on 

 

“Plot_Data”

 

 to see the histogram information: 

Summary of Contents for Data Capture Board CLC-CAPT-PCASM

Page 1: ...Receiver Transmitter an oscillator and a level translator IC The captured data is stored in either three 32K x 8 static RAMs organized into 24 bit words or in a FIFO containing 32K 18 bit words LEDs...

Page 2: ...n board An amplitude of 10 to 16dBm is recommended Here again the HP 8644B is a good choice Software 1 National Semiconductor Software All of the required software is provided on a CD ROM To install t...

Page 3: ...on board pin 20B The third jumper block J2 is unused Data Capture Board Block Diagram DIP Switches Five of the eight DIP switches are used to configure several capture functions as follows DIP switch...

Page 4: ...e Data Capture Board is powered up and the FPGA is initialized it is on to indicate that the board is ready After all the SRAM data has been output it is off LED 2 This LED is on when captured data is...

Page 5: ...ou start with the default file name and location shown Click on Default and then on OK If you do not have a C temp directory please make one The reason for this is that the Matlab script files for dat...

Page 6: ...configuration menu Select Histogram Debug as shown above and click on OK When the data capture control panel returns you can verify your capture settings by positioning the mouse over the progress bar...

Page 7: ...and Capture Board combination require 5V at 1A 4 An IBM Compatible Personal Computer running Windows 95 Windows 98 or Windows NT with a serial port capable of 115 200 baud 5 Serial data cable to conne...

Page 8: ...on The SRAM is useful for displaying time records of data or collecting contiguous blocks of slower data that have been decimated by the CLC5902 DDC The SRAM is the memory element used for the board s...

Page 9: ...rted Next is a discussion of the Mode functions and the related sub functions MODES There are four primary modes in which to run the data capture system each with its own associated options 1 Capture...

Page 10: ...ta source The DRCS Debug data will be displayed at the 15 bit resolution limit this is also the case for the DRCS 24 bit Serial Out data and the histogram will be centered about 16 384 assuming there...

Page 11: ...ditions The main portion of the noise power is contained in the carrier s immediate sidebands 5KHz Another point of interest is that there are several spectral lines about 75dBFS and 25KHz on either s...

Page 12: ...variable to 0 Setting the Dither variable excludes a lower portion of the spectrum from the FFT analysis and is intended to be used in conjunction with a base band dither signal being present at the...

Page 13: ...13 http www national com CLC CAPT PCASM Evaluation Board Layer 1 CLC CAPT PCASM Evaluation Board Layer 2 CLC CAPT PCASM Evaluation Board Layer 3 CLC CAPT PCASM Evaluation Board Layer 4...

Page 14: ...1 1 1 1 6 287 287 287 1 9 9 1 1 1 1 1 1 1 6 6 287 9 9 9 9 5 9 9 9 9 1 4 5 2 2 5 1 57 4 4 9 4 3 3 1 1 5 5 1 2 9 1 4 1 4 602 9 4 1 4 4 4 4 4 4 9 4 4 1 4 4 1 4 56 1 1 1 1 1 865 21 B 21 6 7 7 7 7 7 7 7 7...

Page 15: ...o perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor National Semiconductor National Semicondu...

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