3.0 Functional Description
(Continued)
25
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DP83816
3.10.6 Clock Recovery Module
The Clock Recovery Module (CRM) accepts 125 Mb/s
MLT3 data from the equalizer. The DPLL locks onto the
125 Mb/s data stream and extracts a 125 MHz recovered
clock. The extracted and synchronized clock and data are
used as required by the synchronous receive operations as
generally depicted in Figure 3-8.
The CRM is implemented using an advanced all digital
Phase Locked Loop (PLL) architecture that replaces
sensitive analog circuitry. Using digital PLL circuitry allows
the DP83816 to be manufactured and specified to tighter
tolerances.
3.10.7 NRZI to NRZ
In a typical application, the NRZI to NRZ decoder is
required in order to present NRZ formatted data to the de-
scrambler (or to the code-group alignment block, if the de-
scrambler is bypassed, or directly to the PCS, if the
receiver is bypassed).
3.10.8 Serial to Parallel
The 100BASE-TX receiver includes a Serial to Parallel
converter which supplies 5-bit wide data symbols to the
PCS Rx state machine.
3.10.9 De-scrambler
A serial de-scrambler is used to de-scramble the received
NRZ data. The de-scrambler has to generate an identical
data scrambling sequence (N) in order to recover the
original unscrambled data (UD) from the scrambled data
(SD) as represented in the equations:
Synchronization of the de-scrambler to the original
scrambling sequence (N) is achieved based on the
knowledge that the incoming scrambled data stream
consists of scrambled IDLE data. After the de-scrambler
has recognized 12 consecutive IDLE code-groups, where
an unscrambled IDLE code-group in 5B NRZ is equal to
five consecutive ones (11111), it will synchronize to the
receive data stream and generate unscrambled data in the
form of unaligned 5B code-groups.
In order to maintain synchronization, the de-scrambler
must continuously monitor the validity of the unscrambled
data that it generates. To ensure this, a line state monitor
and a hold timer are used to constantly monitor the
synchronization status. Upon synchronization of the de-
scrambler the hold timer starts a 722
µ
s countdown. Upon
detection of sufficient IDLE code-groups (58 bit times)
within the 722
µ
s period, the hold timer will reset and begin
a new countdown. This monitoring operation will continue
indefinitely given a properly operating network connection
with good signal integrity. If the line state monitor does not
recognize sufficient unscrambled IDLE code-groups within
the 722
µ
s period, the entire de-scrambler will be forced
out of the current state of synchronization and reset in
order to re-acquire synchronization.
3.10.10 Code-group Alignment
The code-group alignment module operates on unaligned
5-bit data from the de-scrambler (or, if the de-scrambler is
bypassed, directly from the NRZI/NRZ decoder) and
converts it into 5B code-group data (5 bits). Code-group
alignment occurs after the J/K code-group pair is detected.
Once the J/K code-group pair (11000 10001) is detected,
subsequent data is aligned on a fixed boundary.
3.10.11 4B/5B Decoder
The code-group decoder functions as a look up table that
translates incoming 5B code-groups into 4B nibbles. The
code-group decoder first detects the J/K code-group pair
preceded by IDLE code-groups and replaces the J/K with
MAC preamble. Specifically, the J/K 10-bit code-group pair
is replaced by the nibble pair (0101 0101). All subsequent
5B code-groups are converted to the corresponding 4B
nibbles for the duration of the entire packet. This
conversion ceases upon the detection of the T/R code-
group pair denoting the End of Stream Delimiter (ESD) or
with the reception of a minimum of two IDLE code-groups.
3.10.12 100BASE-TX Link Integrity Monitor
The 100 Base-TX Link monitor ensures that a valid and
stable link is established before enabling both the Transmit
and Receive PCS layer.
Signal detect must be valid for 395
µ
s to allow the link
monitor to enter the 'Link Up' state, and enable the transmit
and receive functions.
Signal detect can be forced active by setting Bit 1 of the
PCSR.
Signal detect can be optionally ANDed with the de-
scrambler locked indication by setting bit 8 of the PCSR.
When this option is enabled, then De-scrambler 'locked' is
required to enter the Link Up state, but only Signal detect is
required to maintain the link in the link Up state.
3.10.13 Bad SSD Detection
A Bad Start of Stream Delimiter (Bad SSD) is any transition
from consecutive idle code-groups to non-idle code-groups
which is not prefixed by the code-group pair J/K.
If this condition is detected, the DP83816 will assert RXER
and present RXD[3:0] = 1110 to the MAC for the cycles that
correspond to received 5B code-groups until at least two
IDLE code groups are detected. In addition, the False
Carrier Event Counter will be incremented by one.
Once at least two IDLE code groups are detected, the error
is reported to the MAC.
UD
SD
N
⊕
(
)
=
SD
UD
N
⊕
(
)
=
Summary of Contents for DP83816AVNG
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