Connection and Proper Test
Methods
Figure 4 shows a photo of the evaluation board with the con-
nection ports indicated. The PoE circuit occupies the lower
part of the board within the rectangular outline. The RJ45
connectors, Ethernet magnetics and PHY circuit are placed
in the upper area of the board.
The following are the seven connections:
•
J1
, a 42 pin MII Connector for the Ethernet media
independent interface.
•
JE4 through JE7
, double pairs of connection pins for the
3.3V output. JE4 and JE5 of are the high potential pins
•
J13
, a regular RJ45 connector on the -E version board for
PoE input and data link
•
UE13
, Bel Stewart Integrated RJ45 connector on the -I
version board for PoE input and data link
•
TP7 and TP8
, a pair of pins for quick PoE input connection
to a bench power supply. TP7 is the high potential pin
•
P1
, a PJ102A power jack, for Auxiliary (AUX) power input.
The center pin of P1 is the high potential pin
•
TP3 and TP4
, a pair of pins for quick AUX power input
connection to a bench power supply. TP3 is the high
potential pin
20205202
FIGURE 4. The Connection Ports of the Evaluation Board
The -E version evaluation board employs a regular RJ45 con-
nector, J13, which is to be used with the external Ethernet
magnetics assembly U4. The -I version evaluation board uses
an integrated RJ45 connector, UE13, which has the Ethernet
magnetics enclosed in the case.
For the PoE input through either RJ45 connector, the diode
bridge BR1 or BR2 is used to steer the current to the positive
and negative supply pins of the LM5072, namely the VIN and
VEE pins. When using TP7 and TP8 for the quick PoE input
connection to a bench power supply, make sure TP7 is the
high potential terminal.
For the AUX power input, the higher potential should feed into
the center pin of P1. When using TP3 and TP4 for the quick
AUX input connection to a bench power supply, be aware that
TP3 is the high potential pin. The diode DE1 provides the re-
verse protection of the AUX input.
Please note that TP4 and TP8 are two different return pins for
the PoE and AUX inputs, respectively. They are not connect-
ed to the same circuit node, and they should not be inter-
changed.
For the output connection, the load can be either a passive
resistor or active electronic load. Attention should be paid to
the output polarity when connecting an electronic load. It is
not recommended to use additional filter capacitors greater
than 20 µF total across the output port as the extra capaci-
tance will alter the feedback loop properties and may cause
instability. If it is necessary to add extra capacitance in a par-
ticular application, the feedback loop compensation must be
adjusted accordingly.
Sufficiently large wire such as AWG #18 or thicker is required
when connecting the source supply and load. Also, monitor
the current into and out of the circuit board. Monitor the volt-
ages directly at the board terminals, as resistive voltage drops
along the connecting wires may decrease measurement ac-
curacy. Never rely on the bench supply’s voltmeter or amme-
ter if accurate efficiency measurements are desired.
When measuring the dc-dc converter efficiency, the converter
input voltage should be measured across CE4. When mea-
suring the evaluation board overall efficiency (which is more
relevant), both input and output voltages should be read from
the terminals of the evaluation board. Remember to count the
power dissipation by the PHY circuit in the efficiency mea-
surement. When the PHY circuit is in the idle mode, it will draw
55 mA from the 3.3V rail, most of which is consumed by the
on-board LED indicators.
Refer to the appropriate user manual or instruction for the use
of the MII connector.
7
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