If the AUX power option is not used in a new design, delete
CE3, DE1, the eight resistors RE1A through RE1D and RE2A
through RE2D, RE13, RE29, and P1 to lower the BOM cost.
AUX Input “OR-ing” Diode Selection
This diode does not need to be a high speed type since there
is no switching action during operation, however, it should be
a low reverse leakage current device. RE29, a 24.9 k
Ω
resis-
tor is employed on the evaluation board, providing a sinking
path for the leakage current of DE1. It is meant to sink all of
the leakage current of DE1 and prevent a false logic state at
the RAUX pin. Please see the LM5072 datasheet for more
details about the selection of DE1 and RE29.
Flyback Converter Topology
The dc-dc converter stage of the evaluation board features
the flyback topology, which employs the minimum number of
power components to implement an isolated power supply at
the lowest possible cost. Generally, the flyback topology is
best suited for applications of power levels lower than 50W.
When the power level is higher, the forward, push-pull and
bridge topologies will be appropriate candidates.
A unique characteristic of the flyback topology is its power
transformer. Unlike an ordinary power transformer that simul-
taneously transfers the power from the primary to the sec-
ondary, the flyback transformer first stores the energy inside
the transformer while the main switch is turned on, and then
releases the stored energy to the load during the rest of the
cycle. When the stored energy is not completely released be-
fore the main switch is turned on again, it is said that the
flyback converter operates in continuous conduction mode
(CCM). Otherwise, it is in discontinuous conduction mode
(DCM).
Major advantages of CCM over DCM include (i) lower ripple
current and ripple voltage, resulting in smaller input and out-
put filter capacitors; and (ii) lower RMS current, thus reducing
the conduction losses. To keep the flyback converter in CCM
at light load, the transformer’s primary inductance should be
designed as large as is practical.
Major drawbacks of CCM, as compared to DCM, are (i) the
presence of the right-half-plane zero, which may limit the
achievable bandwidth of the feedback loop, and (ii) the need
for slope compensation to stabilize the feedback loop at duty
cycles greater than 50%.
The flyback topology can have multiple secondary windings
for several isolated outputs. One or more of these secondary
channels are normally utilized internally by the converter itself
to provide the necessary bias voltages for the controller. The
transformer uses an EFD20 type core with a primary induc-
tance of 45 µH. The converter runs in CCM at full load over
the entire input voltage range, but it will operate in DCM under
light loads. The LM5072’s built-in slope compensation helps
stabilize the feedback loop when the duty cycle exceeds 50%
in 24V AUX power operation.
A additional transformer winding is used to provide the bias
voltage (VCC) to the LM5072 IC. Although the LM5072 con-
troller includes an internal startup regulator which can support
the bias requirement indefinitely, the transformer winding pro-
duces an output about 2V higher than the startup regulator
output, thus shutting off the startup regulator and reducing the
power dissipation inside the IC. Given the low current limit
value (15 mA nominal) of the high voltage startup regulator,
the VCC line is not meant to source external loads greater
than 3 mA in total. The external load of the VCC line is the
“PoE Power” LED indicating the PoE operation mode.
Factors Limiting the Minimum
Operating Input Voltage
The LM5072 supports operation with as low as 9V AUX power
source. However, limited by the flyback power transformer
design, the minimum AUX voltage of the evaluation board is
22V (voltage drops caused by RE1A and alike and DE1 re-
duce the VIN pin potential to about 20V).
The installed EFD20 type power transformer FA2267-AL is a
low cost, area efficient solution to operate with a wide auxiliary
input voltage range from 24V to 57V. However, it does not
support 24W power operation with the lower input voltage.
Under these conditions the excessive magnetic flux may sat-
urate the transformer core. It is possible to operate with a
lower voltage AUX source, if the output power level is re-
duced. If full power is required under low AUX input voltage,
the power transformer will need to be redesigned. Contact
National Semiconductor for assistance.
PoE Performance Characteristics
PoE INPUT POWER UP SEQUENCE
The PoE power up sequence is as follows. Note that the RTN
pin (IC pin 8) is isolated from the +3.3V RTN output pin of the
evaluation board:
1.
The circuit first enters detection mode.
2.
Depending on the PSE in use, the circuit may or may not
go through classification mode.
3.
The PSE enters full power application mode. Before the
PoE input voltage reaches the UVLO threshold, the hot
swap MOSFET is in the OFF state. Thus, all nodes in the
non-isolated section of the power supply remain at high
potential. The voltage across the hot swap MOSFET,
namely the voltage across the RTN and VEE pins, will be
approximately equal to the PoE input voltage seen
across the VIN and VEE pins.
4.
When the UVLO is released during the PoE input power
up, the drain of the internal hot swap MOSFET is pulled
down to VEE (IC pin 7) gradually as the input current
charges up the input capacitors.
5.
The VCC regulator powers up during the inrush
sequence. During VCC regulator startup, it draws current
on the order of 20mA, but this will likely not be noticed by
the user. Once the RTN pin of the IC drops below 1.5V
(referenced to VEE), and the gate of the hot swap
MOSFET rises, power good is asserted by pulling the
nPGOOD pin low.
6.
Once power good has been asserted, the SS (Soft-Start)
pin is released. The SS pin will rise at a rate equal to the
SS current source, typically 10 µA, divided by the SS pin
capacitance, CE26.
7.
After the soft start is complete, the switching regulator
achieves output regulation, and the converter enters
steady state operation. The auxiliary winding will raise
the VCC voltage to about 10.5V, thus shutting down the
internal regulator and increasing efficiency.
Figure 5 shows key waveforms during a normal PoE power
up sequence. Please note that the PSE used in the test goes
through detection mode, but opts out of classification mode
and directly enters full power application mode.
9
www.national.com
AN-1521
