TSW3070EVM Configuration Options
3
SLWU055A – May 2008 – Revised May 2016
Copyright © 2008–2016, Texas Instruments Incorporated
TSW3070EVM: Amplifier Interface to Current Sink DAC - Arbitrary Waveform
Generator Demonstration
TSW3070EVM (continued)
3
Software Feature Descriptions
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4
Jumper List
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5
Input and Output Connections
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6
Optional Output Signal Path
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1
TSW3070EVM Configuration Options
The TSW3070EVM can be configured to evaluate the two active output stages. This section outlines the
various component configurations. Based on the configuration, testing and board setup must be altered to
accommodate the given components and features.
1.1
DAC Component
The TSW3070EVM uses the 1-GSPS LVDS DAC5682Z with a current sink output.
1.2
Board Configuration
The analog output of the DAC employs a current sink structure which requires the dc common mode of
the DAC to be kept at 3.3 V with a maximum compliance voltage at 3.8 V and a minimum voltage at 2.8 V.
The resistor bias network between the DAC5682Z and the OPA695 or THS3095 assume that the DAC
has maximum current set at 20 mA. For the OPA695 output stage, this network combined with the filter
termination provides a combined ac impedance of about 25
Ω
, resulting in a maximum voltage of 500
mVpp on each DAC output pin. For the THS3091 and THS3095, the network is different and provides a
combined 50-
Ω
load, resulting in a 1-Vpp signal on each of the DAC output pins. By design, in order to
preserve the proper dc levels, the DAC coarse gain should be kept at the maximum (15), though deviation
by a few steps is generally acceptable with no degradation in performance.
The OPA circuits have been designed to have a combined output gain of 2.2x, whereas the THS3091 and
THS3095 circuit has a gain of 3.3x. The resistor networks and gain can be modified as necessary for
custom applications. However, special care must be taken to ensure that the 3.3-Vdc common mode
voltage is maintained at the DAC output and the DAC compliance voltages are met.
1.2.1
Using Optional Passive Transformer Output
The resistor network can be configured such that the DAC output is routed to a transformer which enables
measurements of the DAC output to be made using a passive transformer output. Either of the outputs
can be configured for this (see
1.2.2
Using External Operational Amplifier Supplies
By default, both amplifiers are set up to operate with a ±5 V. This is adequate in most cases for evaluation
purposes. However, both the OPA695 and THS3095 can be operated at higher voltages; the OPA can be
used with a ±6-V supply, and the THS3095 can be used with a ±15-V supply. Ferrite beads allow the use
of a different ±Vamp supply for both amplifiers. If the THS3095 is being evaluated at voltages higher than
±6 V, the OPA695 power ferrite beads should be removed to isolate the OPA695 from the higher supply
voltages (see
1.3
VCXO
The CDCM7005 requires a VCXO source to derive its output clock signals. The VCXO is at reference
designator U6. There is an onboard 10-MHz reference as well as an onboard 800-MHz VCXO. These can
be locked together using the CDCM7005 with the appropriate programming via the DAC5682Z GUI.
An external VCXO clock source can be used. In this mode, the CDCM7005 only acts as a clock divider or
buffer to provide the necessary clocks to the TSW3100 LVDS pattern generator, and sampling clock to the
DAC5682Z.
